M. Declercq

A high-efficiency CMOS voltage doubler

A charge pump cell is used to make a voltage doubler using improved serial switches. A complete power efficiency theory is presented which fits the measurements. The importance of capacitors is shown with plots of power efficiency versus load and stray capacitors. Several problems arising at low voltage or high frequency are developed and some optimizations are presented. The substrate current is totally suppressed by the technique of bulk commutation. A power efficiency of 95% has been reached using external capacitors. A fully integrated charge pump is also presented and shows a maximum power efficiency of 75%.

New encoding scheme for high-speed flash ADC's

A new encoding scheme for high-speed flash analog to digital converters using a Wallace tree is described. It provides a global error filtering and its regular topology optimises the signal propagation. Its application to a 5-bit 1.4-GHz Gallium Arsenide analog-to-digital converter is described.

A new high efficiency CMOS voltage doubler

A charge pump cell is used to make a voltage doubler using improved serial switches. The PMOS transistor used for the serial switch is analyzed and a model suitable for simulation is described. The importance of capacitors is shown with plots of efficiency versus load and stray capacitance. Several problems arising at low voltage or high frequency are developed and some optimizations are presented. The substrate current is totally suppressed by the technique of bulk commutation. An efficiency of 94% has been reached using external capacitors.

Implementation of a learning Kohonen neuron based on a new multilevel storage technique

A compact implementation of a fully parallel Kohonen network with learning capabilities is described. Implementation issues concerning general neural networks are briefly explored, and an original mixed analog and digital technique for storing discrete voltages on a capacitor is presented. The limitations are discussed, and measurements on the storage dynamics are reported, showing that 8 b of resolution can be achieved. This technique is applied to the realization of a neuron dedicated to Kohonen maps. This neuron has been implemented in a standard 2- mu m CMOS technology, and the synaptic functions are very dense. The implementation uses a standard 8-b integer arithmetic. Efficient and consistent encoding of the information, dynamic storage, and the adaptation of the synaptic weights and the synaptic multipliers use simple circuitry, thus leading to a low number of transistors. >

Modeling and design of a low-voltage SOI suspended-gate MOSFET (SG-MOSFET) with a metal-over-gate architecture

A novel MEMS device architecture: the SOI SG-MOSFET, which combines a solid-state MOS transistor and a suspended metal membrane in a unique metal-over-gate architecture, is proposed. A unified physical analytical model (weak, moderate and strong inversions) is developed and used to investigate main electrostatic characteristics in order to provide first-order design criteria for low-voltage operation and high-performance. It is demonstrated that the use of a thin gate oxide (<20 nm) is essential for a high C/sub on//C/sub off/ ratio (>100) and a low spring constant (<100 N/m) is needed for low voltage (<5 V) actuation. An adapted fabrication process is reported.

A fast Modulator for dynamic supply linear RF power amplifier

A fast modulator for a dynamic supply linear RF amplifier has been integrated in a 0.35-/spl mu/m CMOS technology. The use of this modulator with an external linear power amplifier (PA) allows to maintain its efficiency at a higher level than it would with the same PA supplied at constant voltage. The modulator is designed to follow rapid envelope variations at high efficiency without compromising the RF PA linearity.

Few electron devices: towards hybrid CMOS-SET integrated circuits

In this paper, CMOS evolution and their fundamental and practical limitations are briefly reviewed, and the working principles, performance, and fabrication of single-electron transistors (SETs) are addressed in detail. Some of the unique characteristics and functionality of SETs, like unrivalled integration and low power, which are complementary to the sub-20 nm CMOS, are demonstrated. Characteristics of two novel SET architectures, namely, C-SET and R-SET, aimed at logic applications are compared. Finally, it is shown that combination of CMOS and SET in hybrid ICs appears to be attractive in terms of new functionality and performance, together with better integrability for ULSI, especially because of their complementary characteristics. It is envisioned that efforts in terms of compatible fabrication processes, packaging, modeling, electrical characterization, co-design and co-simulation will be needed in the near future to achieve substantial advances in both memory and logic circuit applications based on CMOS-SET hybrid circuits.

Avalanche breakdown in high-voltage D-MOS devices

A new type of voltage breakdown occurring in high-voltage D-MOS transistors is described. This effect severely reduces the high-voltage capability of these devices when the gate field plate is extended through the drift region toward overlapping the n+drain contact region. The breakdown is shown to be due to an avalanche phenomenon appearing close to the n+region, due to the very high field induced in this NIOS structure in nonequilibrium. A first-order theory is developed to confirm the conclusions of the experimental study.

SALIM: a layout generation tool for analog ICs

The authors present a system for analog layout generation of integrated microcircuits (SALIM). The program, which combines a set of algorithms with a knowledge base, features two working modes: automatic and interactive. In the automatic mode, a knowledge-based expert system drives the algorithms. In the interactive mode, the designer task is reduced to the choice of basic elements and their association sequence.<<ETX>>

Load optimization of an inductive power link for remote powering of biomedical implants

This article presents the analysis of the power efficiency of the inductive links used for remote powering of the biomedical implants by considering the effect of the load resistance on the efficiency. The optimum load condition for the inductive links is calculated from the analysis and the coils are optimized accordingly. A remote powering link topology with a matching network between the inductive link and the rectifier has been proposed to operate the inductive link near its optimum load condition to improve overall efficiency. Simulation and measurement results are presented and compared for different configurations. It is shown that, the overall efficiency of the remote powering link can be increased from 9.84% to 20.85% for 6 mW and from 13.16% to 18.85% for 10 mW power delivered to the regulator, respectively.