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Dive into the research topics where B. Jayant Baliga is active.

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Featured researches published by B. Jayant Baliga.


Solid-state Electronics | 1983

Improving the reverse recovery of power mosfet integral diodes by electron irradiation

B. Jayant Baliga; John P. Walden

Abstract This paper demonstrates that controlled electron irradiation of silicon power MOSFET devices can be used significantly improve the reverse recovery characteristics of their integral reverse conducting diodes without adversely affecting the MOSFET characteristics. By using 3 MeV electron irradiation at room temperature it was found that the reverse recovery charge in the integral diode could be continuously reduced in a well controlled manner from over 500 nC to less than 100 nC without any significant increase in the forward voltage drop of the integral diode under typical operating peak currents. The reverse recovery time was also observed to decrease from 3 microseconds to less than 200 nsec when the radiation dose was increased from 0 to 16 Megarads. The damage produced in gate oxide of the MOSFET due to the electron radiation damage was found to cause an undersirable decrease in the gate threshold voltage. This resulted in excessive channel leakage current flow in the MOSFET at zero gate bias. It was found that this channel leakage current was substantially reduced by annealling the devices at 140°C without influencing the integral diode reverse recovery speed. Thus, the electron irradiation technique was found to be effective in controlling the integral diode reverse recovery characteristics without any degradation of the power MOSFET characteristics.


Solid-state Electronics | 1976

Analytical solutions for the breakdown voltage of abrupt cylindrical and spherical junctions

B. Jayant Baliga; Sorab K. Ghandhi

Abstract Analytical solutions for the breakdown voltage of abrupt cylindrical and spherical junctions have been obtained, using suitable approximations for the electric field in the depletion layer. These solutions are shown to be within ±1% of exact computer solutions for doping densities of less thant 10 16 cm −1 . By normalization to the parallel plane case, these solutions have been presented in a form which allows the computation of the breakdown voltage of both cylindrical and spherical junctions using a single curve for each situation.


Solid-state Electronics | 1985

Temperature behavior of insulated gate transistor characteristics

B. Jayant Baliga

Abstract The Insulated Gate Transistor (IGT) is a new power semiconductor device with the high input impedance features of the power MOSFET and the ability to operate at high current densities even exceeding that of power bipolar transistors. The high temperature operating characteristics of the device are discussed here. Unlike the power MOSFET whose operating current density decreases by over a factor of 2 when the ambient temperature is raised to 150°C, the IGT is found to maintain its high operating current density at elevated temperatures. The temperature coefficient of the output current is found to be positive at forward drops below 1.5 V and negative at forward drops above 1.5 V. These characteristics make the IGT suitable for applications with high ambient temperatures. The results also indicate that these devices can be paralleled without current hogging problems if the forward conduction occurs at forward voltage drops in excess of 1.5 V.


Solid-state Electronics | 1977

Optimization of recombination levels and their capture cross section in power rectifiers and thyristors

B. Jayant Baliga; Surinder Krishna

Abstract Single level recombination statistics have been used to determine the influence of lifetime on the characteristics of power rectifiers and thyristors. It is shown that the ratings of rectifiers can be optimized by maximizing the ratio of the high level to the low level lifetime. An optimization criterion relating the recombination center location to its capture cross section ratio for holes and electrons is derived. The relationship is found to be a function of temperature but not dependent upon the resistivity of the base material. In the case of thyristors it is shown that the leakage current must also be considered in the optimization procedure. This leads to a criterion which relates the recombination center location to the resistivity and the capture cross section. In addition, presently used techniques of gold diffusion and electron irradiation are shown to produce levels which fit poorly into the optimization scheme. The work in this paper points out the need to gather more information regarding the energy levels and capture cross sections of other impurities in silicon.


Journal of Crystal Growth | 1977

Morphology of silicon epitaxial layers grown by undercooling of a saturated tin melt

B. Jayant Baliga

Abstract The surface quality of epitaxial silicon layers, grown by the undercooling of a tin melt saturated with silicon, is examined as a function of the growth conditions. It is observed that, at slow cooling rates where the growth is mass-transport controlled, striations are present on thin epitaxial layers and the surface quality improves with increasing layer thickness. As the cooling rate is increased, the surface quality deteriorates due to the formation of ripples on the surface arising from constitutional supercooling effects. At very high cooling rates, the growth becomes kinetically controlled, and the surface quality becomes worse with increasing layer thickness due to the occurrence of vicinal growth with a stepped surface arising from surface misorientation of the substrate qith respect to the (111) plane.


Solid-state Electronics | 1985

Analysis of junction-barrier-controlled Schottky (JBS) rectifier characteristics

B. Jayant Baliga

Abstract This paper provides analytical solutions for the forward conduction and reverse leakage characteristics of junction-barrier-controlled Schottky (JBS) rectifiers. Good agreement between the calculated output characteristics using these solutions and experimental measurements on devices fabricated with different junction depths and Schottky barrier heights is observed. These equations are valuable for the analysis and design of JBS power rectifiers.


Solid-state Electronics | 1979

Grid depth dependence of the characteristics of vertical channel field controlled thyristors

B. Jayant Baliga

Abstract The effect of changing grid depth upon the characteristics of vertical channel field controlled thyristors has been experimentally studied. It is found that increasing the grid depth results in an exponential increase in the differential blocking gain, and a significant decrease in the turn-off time, with no detrimental effect upon the forward conduction characteristics.


Solid-state Electronics | 1982

High gain power switching using field controlled thyristors

B. Jayant Baliga

Abstract A technique for high gain power switching using field controlled thyristors is described. This technique uses a MOSFET connected in series with the FCT to control the current flow. The circuit exhibits normally-off behavior and is capable of operation at high voltages. The current through the FCT can be turned on and off by the application of a low voltage gate signal to the MOSFET. Turn-on and turn-off times of less than 1 μs have been observed at a current gain of over 30. The new gating technique offers the advantage of the large operating current density of the FCT even at high breakdown voltages and the high input impedance of the MOS gate used to trigger the device during power switching.


Solid-state Electronics | 1975

“GAMBIT: GAte Modulated BIpolar Transistor”

B. Jayant Baliga; Douglas E. Houston; Surinder Krishna

Abstract A planar, interdigitated, integrated device structure is described whose characteristics show a voltage controlled negative resistance between two of its terminals. This negative resistance can be controlled by the applied bias to a third terminal. Devices have been fabricated with this structure to achieve negative resistance values ranging from a few hundred thousand ohms down to less than a hundred ohms. The physical mechanisms that give rise to this negative resistance are described and a dc analysis of its behavior is presented. The analysis shows excellent agreement with the observed device characteristics.


Solid-state Electronics | 1978

Recombination level selection criteria for lifetime reduction in integrated circuits

B. Jayant Baliga

Abstract In the past, lifetime control in integrated circuits has been done on an empirical basis. This paper introduces selection criteria for recombination centers which are to be used for reducing minority carrier lifetime in integrated circuits. It is shown that the recombination level should have a large lifetime ratio ( τ SC / τ LL ) in order to obtain minority carrier lifetime reduction with minimal increase in the leakage current, and should possess large capture cross section values in order to minimize compensation effects. Using these criteria, preferred locations for the recombination center have been defined for both p and n type silicon, and the trade-off between reduction of lifetime and increase in leakage current has been shown to degrade with increase in resistivity and ambient temperature. These criteria have also allowed a quantitative comparison between various lifetime control techniques for the first time, and platinum doping has been identified as the most favorable lifetime control process at the present time.

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Sorab K. Ghandhi

Rensselaer Polytechnic Institute

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