B. Lepley

A fast CRC implementation on FPGA using a pipelined architecture for the polynomial division

The CRC error detection is a very common function on telecommunication applications. The evolution towards increasing data rates requires more and more sophisticated implementations. In this paper, we present a method to implement the CRC function based on a pipeline structure for the polynomial division. It improves very effectively the speed performance, allowing data rates from 1 Gbit/s to 4 Gbit/s on FPGA implementations, according to the parallelisation level (8 to 32 bits).

A high speed encoder for recursive systematic convolutive codes

Improving the quality of service is an important target in modern multimedia applications. The main keywords defining the quality of service are the data rate and the data transmission reliability. Error correcting codes are generally employed to achieve the reliability of the data transmission. The present trend is to achieve high data rates on low-cost designs (such as FPGAs). Most of the time, parallel architectures are required to process error correcting codes with high data throughput. In this paper an effective parallel architecture is proposed for recursive convolutive systematic encoders. It is based on parallel and pipelining techniques and can be applied to non-recursive encoders. Data rates up to 693 Gbits/s can be achieved on FPGA implementations.

Fast configurable polynomial division for error control coding applications

The motivation for this paper is the need for high levels of reliability in modern telecommunication systems requiring very high data transmission rates. The search for technologically independent solutions, easy to implement on low cost and popular devices such as FPGA is an important issue. In this paper, we present a method to improve effectively the speed performance of the polynomial division performed in most error detecting and error correcting circuits. It is based on a pipeline structure for the polynomial division. Furthermore, the proposed solution is fully configurable, both from the static and the dynamic points of view. At synthesis stage, the parallelism level (size of the pipeline structure) and the maximal size of the polynomial divisor must both be chosen. Afterwards, the actual divisor can be chosen and changed while the circuit is running. The architecture proved to be very effective, as data rates up to 2.5 Gbits/s have been reached.

A new processor architecture dedicated to digital modem applications

The aim of this paper is to present a new processor architecture designed to cope with most of the functions of a high rate digital modem application. This work is part of an EURICO European project, whose target is the design of a TV cable modem. The paper introduces many of the aspects of the TV cable digital modem application. Functional solutions for many of the application problems are presented. Then, the processor architecture, based on a core processor (core DSP) and on auxiliary dedicated modules (ADM) is described. The architectural choices and the main advantages are discussed.

A high-speed parallel DSP architecture dedicated to digital modem applications

This paper presents the architecture of a high-speed digital signal processor (DSP) designed for high rate digital modem applications. This work stands as a part of an EURICO European project, whose target is the design of a TV cable modem. First, some aspects of the TV cable digital modem application are presented. Then, the paper describes the DSP architecture, based on a VLIW core processor and on auxiliary dedicated modules (ADM). The architectural choices and the main advantages are discussed. Last, the general structure of the ADMs is discussed through an example: the implementation of a cyclic redundancy checking (CRC) dedicated ADM.

A methodology to design a multimedia processor core

Modems and other network interfaces are critical devices in a network infrastructure. While software modems would be the ideal solution for flexibility and low cost, they miss the speed performance requirement. On the other hand, the usual hardware specific approach is not adapted to the fast evolution of protocols in modern multimedia network applications, in which very high data rates, flexibility, reliability and low cost designs are the target keywords. Designing a new processor architecture based on a pseudosystolic MIMD approach is a promising road to explore in order to find an effective trade-off between all these requirements. The aim of this paper is to present a methodology to design such a complex and specific device and to introduce an useful set of CAD (Computer Aided Design) tools.

Fast parallel architecture for syndrome convolutional decoder

This paper presents a parallel architecture for the syndrome convolutional decoder. It is build-up of a parallel convolutional encoder and a syndrome correction block. The proposed architecture combines combinatorial and pipeline parallelism techniques. Using both techniques allows to limit the critical path increase on higher levels of parallelism, i.e. limit the operating frequency decrease. Data rates up to 4.78 Gbits/s have been obtained for a 1/2 -rate code implementation on a FPGA device of the ALTERA Flex10KE family.

A polynomial division pipelined architecture for CRC error detecting codes

Error detection in telecommunication applications is frequently ensured with CRC (Cyclic Redundancy Checking). However, the evolution towards increasing data rates increases the need for more and more sophisticated implementations. In this paper, we present an effective architecture for the CRC function based on a pipelined implementation of the polynomial division. It improves very effectively the speed performance, allowing data rates from 1 Gbit/s to 4 Gbit/s on FPGA implementations, according to the parallelisation level (8 to 32 bit).

Design of a selective digital filter for a DAVIC compliant modem

This paper presents the implementation and the performance evaluation of a digital intermediate frequency (IF) filter dedicated to a DAVIC compliant modem. This work completes several studies comparing the performance of two different designs (analog and digital) for a radio-frequency stage in a modem application. These designs have been evaluated for a particular case defined in the DAVIC recommendation. This study was used as a starting point for the choice of the digital architecture. The main problem to implement such. An architecture is located in the IF stage that must operate at a high frequency. Another problem due to the DAVIC recommendation, is the variation of the sampling frequency which complicates the design of the filter. The verification of this method has been performed using the PTOLEMY software from Berkeley University.

Design of a selective digital filter using the decimation technique

Abstract The implementation of an Intermediate Frequency (IF) filter in Digital Audio-VIsual Council (DAVIC) compliant modems is a particularly complex task. In previous works, we compared the performance of different designs (analog and digital) for the radio-frequency stage in a modem application. These designs have been evaluated for a particular case defined in the DAVIC recommendation. The design limits that were pointed out are mainly due, in the digital approach, to the high frequencies at which the IF stage must operate, and to the variation of the sampling frequency. In this paper, we propose a digital implementation of the IF filter based on the decimation technique. The evaluation of the performance has been performed using the PTOLEMY software from the Berkeley University.