Abbas Dandache

Design and FPGA implementation of a wireless hyperchaotic communication system for secure real-time image transmission

In this paper, we propose and demonstrate experimentally a new wireless digital encryption hyperchaotic communication system based on radio frequency (RF) communication protocols for secure real-time data or image transmission. A reconfigurable hardware architecture is developed to ensure the interconnection between two field programmable gate array development platforms through XBee RF modules. To ensure the synchronization and encryption of data between the transmitter and the receiver, a feedback masking hyperchaotic synchronization technique based on a dynamic feedback modulation has been implemented to digitally synchronize the encrypter hyperchaotic systems. The obtained experimental results show the relevance of the idea of combining XBee (Zigbee or Wireless Fidelity) protocol, known for its high noise immunity, to secure hyperchaotic communications. In fact, we have recovered the information data or image correctly after real-time encrypted data or image transmission tests at a maximum distance (indoor range) of more than 30 m and with maximum digital modulation rate of 625,000 baud allowing a wireless encrypted video transmission rate of 25 images per second with a spatial resolution of 128 × 128 pixels. The obtained performance of the communication system is suitable for secure data or image transmissions in wireless sensor networks.

A fast CRC implementation on FPGA using a pipelined architecture for the polynomial division

The CRC error detection is a very common function on telecommunication applications. The evolution towards increasing data rates requires more and more sophisticated implementations. In this paper, we present a method to implement the CRC function based on a pipeline structure for the polynomial division. It improves very effectively the speed performance, allowing data rates from 1 Gbit/s to 4 Gbit/s on FPGA implementations, according to the parallelisation level (8 to 32 bits).

Smart Reliable Network-on-Chip

In this paper, we present a new network-on-chip (NoC) that handles accurate localizations of the faulty parts of the NoC. The proposed NoC is based on new error detection mechanisms suitable for dynamic NoCs, where the number and position of processor elements or faulty blocks vary during runtime. Indeed, we propose online detection of data packet and adaptive routing algorithm errors. Both presented mechanisms are able to distinguish permanent and transient errors and localize accurately the position of the faulty blocks (data bus, input port, output port) in the NoC routers, while preserving the throughput, the network load, and the data packet latency. We provide localization capacity analysis of the presented mechanisms, NoC performance evaluations, and field-programmable gate array synthesis.

Designing fault-secure parallel encoders for systematic linear error correcting codes

We consider the open problem of designing fault-secure parallel encoders for various systematic linear ECC. The main idea relies on generating not only the check bits for error correction but also, separately and in parallel, the check bits for error detection. Then, the latter are compared against error detecting check bits which are regenerated from the error correcting check bits. The detailed design is presented for encoders for CRC codes. The complexity evaluation of FPGA implementations of encoders with various degrees of parallelism shows that their fault-secure versions compare favorably against their unprotected counterparts both with respect to complexity and the maximal frequency of operation. Future research will include the design of FS decoders for CRC codes as well as the generalization of the presented ideas to design of FS encoders and decoders for other systematic linear ECC like nonbinary BCH codes and Reed-Solomon codes.

Real-time FPGA implementation of Lorenz's chaotic generator for ciphering telecommunications

In this paper, we present a new approach for realtime FPGA implementation of the random key based Lorenzs chaotic generator for data stream encryption. We propose a structural hardware architecture designed for a small chip area and high speed performance. This architecture is particularly attractive since it provides a low-cost security telecommunication solution while holding or increasing the encryption throughput rate. We show its feasibility through implementation which is detailed and presented using Virtex Xilinx FPGA. This architecture employs only 1926 slices and allows achieving a random key throughput rate of 124 Mbps by using a low system clock with a frequency of up to 15,5 MHz allowing low power consumption especially for embedded applications.

Experimental performance of mobile DVB-T2 in SFN and distributed MISO network

Digital Video Broadcasting-Handheld (DVB-H) and Terrestrial Digital Multimedia Broadcasting (T-DMB) are the most known standards that enable digital television transmissions to handheld or mobile receivers in Europe. The emerging DVB-T2 standard enables a network based on frequency diversity coding (called Alamouti Space-Frequency coding) suitable for multipath propagation environments which presents better performances for fixed reception compared to SFN (Single Frequency Network). In this paper, we present detailed experimental performance results of classical mobile channel (TU6) for DVB-T2. These evaluations are given for different Doppler frequencies in a classical SFN (Single Frequency Network) compared to distributed MISO. Laboratory and field measurements are presented. With the receiver used for our experiments, the results show clearly the quality degradation of received signals for distributed MISO compared to classic SFN. These results are useful for the study and the determination of the current mobile performance of DVB-T2 and network design and may also be useful for upcoming standards such as DVB-NGH (Next Generation Handheld).

A high speed encoder for recursive systematic convolutive codes

Improving the quality of service is an important target in modern multimedia applications. The main keywords defining the quality of service are the data rate and the data transmission reliability. Error correcting codes are generally employed to achieve the reliability of the data transmission. The present trend is to achieve high data rates on low-cost designs (such as FPGAs). Most of the time, parallel architectures are required to process error correcting codes with high data throughput. In this paper an effective parallel architecture is proposed for recursive convolutive systematic encoders. It is based on parallel and pipelining techniques and can be applied to non-recursive encoders. Data rates up to 693 Gbits/s can be achieved on FPGA implementations.

Fast configurable polynomial division for error control coding applications

The motivation for this paper is the need for high levels of reliability in modern telecommunication systems requiring very high data transmission rates. The search for technologically independent solutions, easy to implement on low cost and popular devices such as FPGA is an important issue. In this paper, we present a method to improve effectively the speed performance of the polynomial division performed in most error detecting and error correcting circuits. It is based on a pipeline structure for the polynomial division. Furthermore, the proposed solution is fully configurable, both from the static and the dynamic points of view. At synthesis stage, the parallelism level (size of the pipeline structure) and the maximal size of the polynomial divisor must both be chosen. Afterwards, the actual divisor can be chosen and changed while the circuit is running. The architecture proved to be very effective, as data rates up to 2.5 Gbits/s have been reached.

Robust chaotic key stream generator for real-time images encryption

In this paper, we propose a robust and compact design architecture of hardware chaotic key generator for real-time images encryption. The new proposed approach combines the perturbation technique with a non-linear switching between multiple three-dimensional continuous chaotic systems. The originality of this new scheme is that it allows a low-cost image encryption for embedded systems while still providing a good trade-off between performance and hardware resources. This pipelined architecture is particularly attractive since it provides a high security. Numerical simulations and real-time experimental results using Xilinx FPGA Virtex technology have demonstrated the feasibility and the efficiency of our secure solution and can be applied to many secure real-time embedded applications in System on Chip (SoC). Thorough experimental tests are carried out with detailed analysis, demonstrating the high security and fast encryption speed of the new scheme while still able to resist statistical and key analysis attacks.

Modeling and performance evaluations of Alamouti technique in a single frequency network for DVB-T2

Alamouti space–frequency coding provides additional frequency diversity, especially in multipath propagation environments. This article addresses a new modeling of the Alamouti code multiple input single output (MISO) in a single frequency network(SFN) for two, three, and four transmitters, and different types of coding and modulations in the DVB-T2 (Digital Video Broadcasting Terrestrial second generation). Classical SFN, Alamouti MISO, and combined SFN with Alamouti MISO (called SFN-2x1 Alamouti MISO) are compared and analyzed. Performance evaluations are made for two, three, or four transmission antennas through 0-dB Echo profile, TU6 mobile channel, unbalanced received power and rotated constellation. The obtained results show clearly that the performance of an SFN network using 0-dB Echo profile with Alamouti MISO is only better than a pure SFN for two and three antennas. Moreover, an SFN based on four antennas (receiving from four antennas) has almost the same performance as SFN-2x1 Alamouti MISO.