B.-U.H. Klepser

Analytical bias dependent noise model for InP HEMT's

A practical device model for both high frequency small signal and noise behavior of InP-HEMTs depending on both gate and drain voltage has been developed. The model is based on the two-piece linear approximation using charge control and saturation velocity models. Combining large signal model and analytical expressions for the noise source parameter P, R, and C, an analytical bias-dependent noise model can be obtained. For implementation into high frequency simulation software, the exact calculated bias dependence was mathematically fitted by elementary functions. It could be shown that lowest noise is observed when the drain current for maximum gain is reduced to a third while the drain voltage is reduced to the start of the saturation region V/sub ds/=0.6 V. Modeling scaling effects of the noise behavior shows that lowest noise is observed for a gate width of 1/spl times/40 /spl mu/m. Multi-finger layouts are preferable for gate widths above 70 /spl mu/m. Furthermore it is shown, that the optimum width of each finger decreases with the number of fingers. >

High speed, monolithically integrated pin-HEMT photoreceiver fabricated on InP with a tunable bandwidth up to 22 GHz using a novel circuit design

High speed monolithically integrated photoreceivers were fabricated showing flat photo response and a state of the art bandwidth of 18 GHz, which should be sufficient for data transmission systems well beyond 20 Gbit/s. The circuitry consists of a high input impedance front-end design followed by an equalizing second stage to compensate the input capacitance. A state of the art input noise current of 12 pA//spl radic/Hz within the bandwidth was obtained. The bandwidth of the photoreceiver can be tuned with the bias voltages. For a 3 dB peak at 15 GHz a total bandwidth of 22 GHz was obtained.

Comparison and optimisation of different ohmic contact metallisations for InP-HEMT structures with doped and undoped cap-layers

A direct comparison was made between several ohmic contact metallisations using Ni, Ge and Au for InP based HEMT applications. HEMT structures with both doped and undoped GaInAs cap-layers were investigated. Ni-Ge-Au proved to be the most suitable contact for both structures. An optimum nickel thickness of 100 /spl Aring/ Ni followed by 500 /spl Aring/ Ge and 800 /spl Aring/ Au was found. The contact resistances of the optimised Ni-Ge-Au structure were as low as 0.09 /spl Omega/mm and relatively insensitive to anneal time and temperature and are therefore most suitable for IC fabrication. For applications where high anneal temperatures are required, Ge-Ni-Au ohmic contacts show the largest process window for the anneal temperature. Furthermore it is reported that the contact resistance is independent of the doping of the thin (50-100 /spl Aring/) cap-layer. This indicates that it is the bandgap and not the doping of the cap-layer, which determines the contact resistance to the HEMT structure.<<ETX>>

Frequency analysis of the kink effect in AlInAs/GaInAs HEMTs

A frequency analysis of the transconduction and output conduction of 0.25 /spl mu/m InP based HEMTs was carried out using S-parameter measurements down to 1 kHz. The advantage of this method is that very low frequency and hf performance is determined using a single measurement sequence. It has been shown that the kink effect in the output characteristics consists of two ranges of a reduced and an increased drain current. Additionally it was found, that while g/sub d,hf/ increases for more positive gate voltages, g/sub d,dc/ usually decreases. It has also been shown, that the dc measured transconductance g/sub m,dc/ is lower than g/sub m,hf/. This difference is increased for high drain voltages. The frequency analysis shows that g/sub m,dc/ is generally decreased at higher drain voltages. Finally, it has been shown that the dispersion output conduction can be up to the GHz range for high drain source voltages.

Influence of cap-layer doping on ohmic contacts for InP based hemt structures

Abstract Ohmic contacts to lattice matched InP based HEMT structures with both doped and undoped GaInAs cap-layers have been investigated. Contact resistances as low as 0.09 Ωmm were achieved using annealed NiGeAu ohmic contacts. It is reported that the contact resistance is independent of the doping of the thin (50–100 A) cap-layer. This indicates that it is the bandgap and not the doping of the cap-layer, which determines the contact resistance to the HEMT structure. Furthermore it was shown, that the contact resistance is reduced for lower sheet resistances of the 2DEG.

Low noise optimization of InP HEMTs

The influence of the noise figure on both gate and drain source voltage, threshold voltage and transistor size have been investigated for the design of low noise integrated circuits. Therefore, a device model for both high frequency small signal and noise behavior of InP-HEMTs, depending on both gate and drain voltage, has been developed. It was found that the lowest noise is observed when the drain current for maximum gain is reduced to a third while the drain voltage is reduced to the start of the saturation region V/sub ds/=0.6 V. However, it was shown for the first time that the bias for lowest noise is frequency dependent. Modeling scaling effects of the noise behavior shows, that lowest noise is observed for a gate width of 1/spl times/40 /spl mu/m. Multi-finger layouts are preferable for gate widths above 70 /spl mu/m. Furthermore, it is shown that the optimum width of each finger decreases with the number of fingers.

Monolithically integrated InP-based pin-HEMT OEIC receiver with a bandwidth of 18 GHz

Summary form only given. High-speed photoreceivers are required for multigigabit/s transmission systems. For higher data rates, monolithically integrated photoreceivers offer the advantage of improved performance resulting from the reduction of parasitic capacitances and inductances. Pin-HEMT integration was chosen for this work because, at the present time, InP-based HEMTs have the highest cut-off frequencies and the lowest noise of all three terminal devices.

Low noise performance of dry etched InGaAs/InAlAs HEMTs in comparison with wet recessed devices

Lattice-matched InAlAs/InGaAs HEMTs with selectively dry etched and wet etched gate recesses have been fabricated and both high-frequency and noise measurements have been carried out. The modelling of the noise source parameters shows only minor difference between the two transistor types. There is no evidence of detrimental effects caused by dry etching that reduce the noise performance of the device at high frequencies. To our knowledge, this is the first report of low-noise performance for dry etched InP HEMTs.

Modelling of low noise InP based HEMTs

A device model for both high frequency small signal and noise behaviour of InP-HEMTs, depending on both gate and drain source voltage has been developed. It could be shown, that the optimum gate bias for low noise is, when the drain current is reduced to one third the value required for maximum gain. However, it was found that the optimum gate source voltage is frequency dependent. Regarding the source drain voltage, lowest noise is observed at the start of the saturation region, i.e. Vds, = 0.6 V. Since the model includes not only the intrinsic channel and induced gate noise sources but also Johnson noise of the extrinsic elements, it can be used to model scaling effects of the noise behaviour. It could be shown, that lowest noise is observed for a single-finger HEMT with a gate width of 40 ¿m. Multi-finger layouts are preferable for gate widths above 70 ¿m.

Approach for developing a large signal model of a 150 GHz HEMT

In this contribution the development of a large signal model describing the electrical behaviour of an InAlAs/InGaAs/InP-HEMT will be discussed. The transistors under question were fabricated at our laboratory. They revealed a transit frequency of 150 GHz, which is, to our knowledge, the best result obtained with a T-gate of 0.25 /spl mu/m footprint. The aim of this project was to develop a model of this transistor for simulating nonlinear circuits with commercial simulator software like HP-MDS or Spice. The procedure results in an easily applicable model which produces very good fits to the measured S-parameters.