M. Schefer

Analytical bias dependent noise model for InP HEMT's

A practical device model for both high frequency small signal and noise behavior of InP-HEMTs depending on both gate and drain voltage has been developed. The model is based on the two-piece linear approximation using charge control and saturation velocity models. Combining large signal model and analytical expressions for the noise source parameter P, R, and C, an analytical bias-dependent noise model can be obtained. For implementation into high frequency simulation software, the exact calculated bias dependence was mathematically fitted by elementary functions. It could be shown that lowest noise is observed when the drain current for maximum gain is reduced to a third while the drain voltage is reduced to the start of the saturation region V/sub ds/=0.6 V. Modeling scaling effects of the noise behavior shows that lowest noise is observed for a gate width of 1/spl times/40 /spl mu/m. Multi-finger layouts are preferable for gate widths above 70 /spl mu/m. Furthermore it is shown, that the optimum width of each finger decreases with the number of fingers. >

Integrated coplanar mm-wave amplifier with gain control using a dual-gate InP HEMT

A variable gain mm-wave amplifier, based on InP HEMT devices, is demonstrated. The measured gain control range of 14 dB is the largest reported in the mm-wave range for a monolithically integrated variable gain amplifier. The two stage circuit consists of a single gate transistor and a dual-gate transistor. The circuit has a maximum gain of 22 dB at 44 GHz and a bandwidth of 14.6 GHz. The circuit was fabricated in coplanar technology.

Monolithic V-band high power and varactor tunable HEMT oscillators

The design, fabrication, and the measured results of V-band monolithically integrated fundamental oscillators are presented. The active device is a 0.2 /spl mu/m InP based HEMT with f/sub max/=200 GHz and f/sub t/=100 GHz. A basic V-band oscillator, a high power and a varactor tuned oscillator are compared. The resonance frequency of the basic oscillator is 54.333 GHz and the phase noise -70 dBc/Hz @ 1 MHz offset. The high power oscillator shows 83 dBm output power at 48 GHz For the varactor tunable oscillator an output power of 0 dBm at 63 GHz and a tuning range of 100 MHz are measured. The circuits were fabricated in coplanar technology.

Passive, coplanar V-band HEMT mixer

A passive V-band mixer is presented which uses an InP HEMT for mixing. The measured minimum conversion loss is 10.3 dB (RF 61 GHz, LO 60 GHz) with an LO power of 6 dBm. The circuit was fabricated in coplanar technology.

Low noise optimization of InP HEMTs

The influence of the noise figure on both gate and drain source voltage, threshold voltage and transistor size have been investigated for the design of low noise integrated circuits. Therefore, a device model for both high frequency small signal and noise behavior of InP-HEMTs, depending on both gate and drain voltage, has been developed. It was found that the lowest noise is observed when the drain current for maximum gain is reduced to a third while the drain voltage is reduced to the start of the saturation region V/sub ds/=0.6 V. However, it was shown for the first time that the bias for lowest noise is frequency dependent. Modeling scaling effects of the noise behavior shows, that lowest noise is observed for a gate width of 1/spl times/40 /spl mu/m. Multi-finger layouts are preferable for gate widths above 70 /spl mu/m. Furthermore, it is shown that the optimum width of each finger decreases with the number of fingers.

Low noise performance of dry etched InGaAs/InAlAs HEMTs in comparison with wet recessed devices

Lattice-matched InAlAs/InGaAs HEMTs with selectively dry etched and wet etched gate recesses have been fabricated and both high-frequency and noise measurements have been carried out. The modelling of the noise source parameters shows only minor difference between the two transistor types. There is no evidence of detrimental effects caused by dry etching that reduce the noise performance of the device at high frequencies. To our knowledge, this is the first report of low-noise performance for dry etched InP HEMTs.

Modelling of low noise InP based HEMTs

A device model for both high frequency small signal and noise behaviour of InP-HEMTs, depending on both gate and drain source voltage has been developed. It could be shown, that the optimum gate bias for low noise is, when the drain current is reduced to one third the value required for maximum gain. However, it was found that the optimum gate source voltage is frequency dependent. Regarding the source drain voltage, lowest noise is observed at the start of the saturation region, i.e. Vds, = 0.6 V. Since the model includes not only the intrinsic channel and induced gate noise sources but also Johnson noise of the extrinsic elements, it can be used to model scaling effects of the noise behaviour. It could be shown, that lowest noise is observed for a single-finger HEMT with a gate width of 40 ¿m. Multi-finger layouts are preferable for gate widths above 70 ¿m.

Approach for developing a large signal model of a 150 GHz HEMT

In this contribution the development of a large signal model describing the electrical behaviour of an InAlAs/InGaAs/InP-HEMT will be discussed. The transistors under question were fabricated at our laboratory. They revealed a transit frequency of 150 GHz, which is, to our knowledge, the best result obtained with a T-gate of 0.25 /spl mu/m footprint. The aim of this project was to develop a model of this transistor for simulating nonlinear circuits with commercial simulator software like HP-MDS or Spice. The procedure results in an easily applicable model which produces very good fits to the measured S-parameters.