Badih El-Kareh

Analog characteristics of metal-insulator-metal capacitors using PECVD nitride dielectrics

The frequency dependence of PECVD nitride and LPCVD oxide metal-insulator-metal (MIM) capacitors is investigated with special attention for precision analog applications. At measurement frequencies of 1.0 MHz, nitride MIM capacitors show capacitance linearity close to that of oxide MIM capacitors, indicating potential for precision analog circuit applications. Due to dispersion effects, however, nitride MIM capacitors show significant degradation in capacitor linearity as the frequency is reduced, which leads to accuracy limitations for precision analog circuits. Oxide MIM capacitors are essentially independent of frequency.

An experimental 1-Mbit CMOS SRAM with configurable organization and operation

A 1-Mb SRAM (static random-access memory) configurable as a 128-kb*8, 256-kb*4, or 1-Mb*1 memory featuring asynchronous operation with static-column and chip-enable-access speedup modes or synchronous operation with a fast-page (toggle) or static-column mode is described. It has been fabricated in a double-metal, double-polysilicon CMOS process with 0.7- mu m geometry and special SRAM structures. The measured synchronous access of 29 ns with a fast-page mode access of 22 ns. Measured asynchronous access is 34 ns with a static-column access of 33 ns and a chip-select speedup access of 29 ns. The SRAMs six-transistor CMOS memory cell is 58.24 mu m/sup 2/. >

Low-temperature CMOS-a brief preview

The advantages of operating CMOS at liquid nitrogen temperature (LN) are attributed to increased carrier mobility, reduced subthreshold swing, increased conductivity, reduced leakage, an improved device and circuit reliability such as electromigration ionic migration, and latchup. The gain in performance compared to room temperature (RT), however, begins to erode as the channel length is decreased below one micrometer, where increased lateral field causes the drift velocity to approach its scattering limited value along a large fraction of the channel. In the limit when saturation velocity is reached along the entire channel, the improvement at LN does not exceed a factor of approximately=2, after all other enhancements are considered. This gain must justify the added inconvenience and cost of operating the system at LN temperatures. As the channel length is reduced to deep submicrometer, below approximately=0.15 mu m, operating at low temperature could become a necessity rather than mere improvement over RT, because of the lack of a room-temperature process and device design point. >

The effects of radiation on 1/f noise in complementary (npn+pnp) SiGe HBTs

We present the first study of the effects of radiation on low-frequency noise in a novel complementary (npn+pnp) silicon-germanium (SiGe) HBT BiCMOS technology. In order to manipulate the physical noise sources in these complementary SiGe HBTs, 63.3 MeV protons were used to generate additional (potentially noise-sensitive) trap states. The base currents of both the npn and pnp SiGe HBTs degrade with increasing proton fluence, as expected, although in general more strongly for the npn transistors than for the pnp transistors, particularly in inverse mode. For the pnp SiGe HBTs, irradiation has almost no effect on the 1/f noise to proton fluence as high as 5.0/spl times/10/sup 13/ p/cm/sup 2/, while the npn SiGe HBTs show substantial radiation-induced excess noise. In addition, unlike for the pnp devices, which maintain an I/sub B//sup 2/ bias dependence, the 1/f noise of the post-irradiated npn SiGe HBTs change to a near-linear dependence on I/sub B/ at low base currents following radiation. That suggests a fundamental difference in the noise physics between the two types of devices.

Yield management in microelectronic manufacturing

Semiconductor technology trends continue to drive toward cheaper, faster, denser, lower-power, and more reliable products. These trends are however, neither independent of nor conducive to each other. Faster and denser designs, for example, increase power, reduce yield and reliability, and increase cost. In many cases, a trade-off is made between cost and performance. The prime factor in determining the cost of a product is its manufacturing yield. It has hence become increasingly important to understand the intricate relationships between process technology, product design, manufacturing tools, and yield. The ability to predict yield long before the product is manufactured is fundamental to a decision-making process during the development phase. Accelerated yield-learning is the next step to reducing the development-to-market time and product cost. Several disciplines should progress coherently to define a yield plan and assure meeting the desired yield targets. Special test structures are designed and tested for yield at different stages of the process to determine the dominant yield detractors, the nature of defects, their size and spatial distributions, and their impact on yield. Models are developed to extract yield parameters from test results and predict the product yield. Systematic and gross defects are mostly eliminated early in the development. The impact of random defect size and density increases with minimum feature size. Tool, process, and design changes are hence made to reduce the defect density to a level that can be tolerated by the specific design. Yield learning is vigorously pursued via measurements against the targets, establishing action plans and tightening the targets in a cyclical mode. The purpose of this paper is to describe the yield management methodology and to provide an overview of the steps required to analyze, predict, and accelerate the product yield learning. Practical examples based on memory and logic designs are discussed.

Design of precision capacitors for analog applications

The authors describe and analyze two capacitors which are incorporated in a baseline BiCMOS technology without added process complexity. The first capacitor is formed between degenerated doped polysilicon and silicon. The second is formed between two degenerately doped polysilicon layers. In both structures, the insulator is a deposited or grown oxide. The sensitivity of the capacitor voltage coefficient to oxide thickness and surface dopant concentration is discussed theoretically and compared to measured data. The two capacitors are optimized to exhibit very low voltage coefficients.<<ETX>>

The Effects of Proton and X-Ray Irradiation on the DC and AC Performance of Complementary (npn + pnp) SiGe HBTs on Thick-Film SOI

The impact of 63.3 MeV proton and 10 keV X-ray irradiation on the DC and AC performance of complementary SiGe HBTs on thick-film SOI is investigated. Proton and X-ray induced changes in the forward and inverse Gummel characteristics, the output characteristics, and avalanche multiplication are reported for both npn and pnp SiGe HBTs, at both room temperature (300 K) and at cryogenic temperatures (down to 30 K). Comparison of room temperature and cryogenic data suggests interface trap formation at two distinct physical locations in the transistors. Experimental data and calibrated TCAD simulations are used to compare the radiation response of both thick-film SOI devices and thin-film SOI SiGe HBTs.

A fundamental performance limit of optimized 3.3-V sub-quarter-micrometer fully overlapped LDD MOSFET's

The direct experimental quantification of the relationship between gate-to-drain capacitance (C/sub gd/) and hot-electron reliability (HER) for fully overlapped LDD (FOLD) n-channel MOSFETs (NFETs) is reported. To broaden the applicability and achieve a wide range of FOLD finger lengths, the results are based on devices built using each of three different fabrication techniques. The experimentally observed tradeoff is compared to theoretical calculations to investigate its general and fundamental nature. It is shown that a peak in performance occurs at L/sub eff/ approximately=0.20 mu m for reliable 3.3-V NFETs with T/sub ox/=10 nm. Below 0.20 mu m, performance decreases due to the addition of the large FOLD fingers required to maintain adequate HER. This peak in performance can be shifted to L/sub eff/ approximately=0.15 mu m by introducing FOLD fingers only at the drain end of NFETs. For channel lengths greater than 0.25 mu m, the performances of 3.3-V FOLD NFETs and scaled 2.5-V single-diffusion NFETs are nearly equal. However, 2.5-V single-diffusion NFETs begin to offer a significant performance advantage over 3.3-V FOLD NFETs as channel lengths are reduced below 0.25 mu m. >

An investigation of low-frequency noise in complementary SiGe HBTs

We present a comprehensive investigation of low-frequency noise behavior in complementary (n-p-n + p-n-p) SiGe heterojunction bipolar transistors (HBTs). The low-frequency noise of p-n-p devices is higher than that of n-p-n devices. Noise data from different geometry devices show that n-p-n transistors have an increased size dependence when compared with p-n-p transistors. The 1/f noise of p-n-p SiGe HBTs was found to have an exponential dependence on the (intentionally introduced) interfacial oxide (IFO) thickness at the polysilicon-to-monosilicon interface. Temperature measurements as well as ionizing radiation were used to probe the physics of 1/f noise in n-p-n and p-n-p SiGe HBTs. A weak temperature dependence (nearly a 1/T dependence) of 1/f noise is found in both n-p-n and p-n-p devices with cooling. In most cases, the magnitude of 1/f noise is proportional to I/sub B//sup 2/. The only exception in our study is for noise in the post-radiation n-p-n transistor biased at a low base current, which exhibits a near-linear dependence on I/sub B/. In addition, in proton radiation experiments, the 1/f noise of p-n-p devices was found to have higher radiation tolerance than that of n-p-n devices. A two-step tunneling model and a carrier random-walk model are both used to explain the observed behavior. The first model suggests that 1/f noise may be caused by a trapping-detrapping process occurring at traps located inside IFO, while the second one indicates that noise may be originating from the emitting-recapturing process occurring in states located at the monosilicon-IFO interface.

Silicon on insulator-an emerging high-leverage technology

Silicon on insulator (SOI) has emerged as a high-leverage technology for a wide range of commercial and military applications. While the use of SOI is presently limited to special niche applications, such as radiation-hard space and defense electronics, thin-film SOI has become strategic for low-power, battery-operated portable systems and large-scale integrated logic and memory circuits with sub-half micron features. Substantial process simplification and cost reduction result from the dielectrically isolated structures. Other important SOI applications are the merger of several functions on the same die that performs reliably in adverse high-temperature environments. These include analog and logic functions, smart micromechanical sensors for automotive and distributed jet engine control with logic functions, or smart high-voltage CMOS logic/control elements. Manufacturable solutions to several material and device problems, however, must be demonstrated before SOI CMOS or BiCMOS designs enter the high-volume commercial manufacturing stage. Among these are the availability, cost, and quality of SOI material, gettering, electrostatic discharge protection, the floating-body problem in thin-film structures, and self-heating effects caused by the low thermal conductivity of the buried-oxide layer. The status of SOI material is discussed, including the different methods used to prepare large SOI wafers, wafer availability, cost reduction strategies, material characterization, and material quality. Applications and leverage areas are also described, with emphasis on problems and challenges that lie ahead for the large-scale manufacture of SOI products. The potential economic impact of SOI technology on the profitability of semiconductor manufacturing is described. >