Baher Haroun

A novel reduced swing CMOS bus interface circuit for high speed low power VLSI systems

Major applications of CMOS VLSIs require the use of high fan out busses, such as Asynchronous Transfer Mode (ATM) cross-bar switching matrices, high performance processors employing multiple busses, and high performance CPLDs using universal interconnection matrices. The bus interface circuits are major contributors to the power dissipation of a system for achieving high clocking frequencies. To address the increased power dissipation for high speed busses, a novel reduced voltage swing CMOS bus interface circuit is presented here. The design is a combination of drivers and receivers which perform level translation without any need to reduce the supply voltage. The simulation results based on these circuits show significant enhancements on both speed and power in comparison with the conventional CMOS tri-state driver techniques. To further assess this design, an LSI 32/spl times/32 crosspoint switch is implemented to be used for ATM communication systems. The chip uses a 1.2 /spl mu/m CMOS process with a die size of 4/spl times/3 mn, and has pseudo ECL input/output compatible interfaces which can operate at 250 Mb/s serial communication links per channel. The power consumption at 250 Mb/s is 0.6 W which is 60% lower than other published results for a similar switch. Without the input/output pad restrictions, the simulation results indicate that the switching matrix is capable of running at 622 Mb/s with a similar power reduction.<<ETX>>

Power estimation tool for sub-micron CMOS VLSI circuits

Accurate and fast time-domain current waveform simulation is important for the design of reliable CMOS VLSI circuits. A detailed current model that resulted in a maximum of 10% deviation from the current waveforms as obtained by SPICE LEVEL 3 at peak values and 5% at the average current is presented. The current model accounts for short-channel effects, input risetimes, short-circuit and dynamic current, and circuit topology. Moreover, the model produces piecewise linear current waveforms and can be incorporated in any switch-level simulator. Using the models in an event driven simulator, a 3-4 orders of magnitude speedup relative to SPICE LEVEL 3 has been achieved. The results for current waveform accuracy are better than those obtained for previously published methods and in particular for complex CMOS circuits.<<ETX>>

ILP synthesis of signal processing architectures with minimum structural complexity

In this paper, we present details of an integer linear programming (ILP) formulation for combined scheduling and operation bindings. The formulation is suitable for multiplexer based datapaths. A novel formulation and optimization criteria that minimizes structural complexity of the final datapath is presented. Architectural results having considerably lower interconnections and mux inputs than previous ILP solutions are shown for typical signal processing synthesis benchmarks.<<ETX>>

Synthesis of multiple bus/functional unit architectures implementing neural networks

An automated architectural synthesis methodology for implementing digital neural networks is presented. The synthesis approach uses heuristics and is based on VLSI multiple-bus/functional-unit architectures with internal parallelism. The synthesis methodologies and tradeoffs as well as the features of the architectures are presented. The architectures resulting from the synthesis tool outperform other architectures for the same applications.<<ETX>>

Architectural synthesis for digital neural networks

Using automated synthesis techniques, the design cycle of digital implementations of neural networks can be reduced and the design space can be reduced and the design space can be extensively searched. This will lead to the development of inexpensive commercial hardware for neural real time applications that satisfy response time and silicon area constraints. The authors present an automated architectural synthesis methodology for implementing digital neural networks. The synthesis approach and the trade-offs involved in the designs are presented. The synthesis is based on VLSI multiple-bus/functional unit architectures with internal parallelism. The functional units used in these architectures, their components, and features are discussed. Examples of various architectures for backpropagation and counterpropagation neural networks used in robotic and signal processing applications are also presented.<<ETX>>

Floorplanning with datapath optimization

This paper presents a floorplanner for datapath with the capability of re-allocating data storage for minimizing the interconnect area and critical path delay without altering the number of functional units and the schedule. The tool has combined two novel approaches: 1-A placement and routing model to handle different architectural topologies (mux. and/or bus based) suitable for FPGAs. 2-An efficient formulation for the binding of register/interconnect and combined floorplanning. The complexity of the architectural and floorplanning model, and of the cost function, have led us to the use of a stochastic optimization process. The running time of the whole process indicates the viability of the method. We show through various examples how the floorplanner improves the area and critical path delay of the datapath compared to a plain floorplanner. The improvement is about 20% for the critical path delay when this objective is a stringent constraint.

A floorplanner driven by structural and timing constraints

This paper presents a novel layout model and floorplanning tool particularly suitable for taking into account user defined layout constraints on specific sets of modules and specific locations. The user defined layout constraints can be the setting of any common topological property associated with a group of specific modules such as the neighboring property for example. Or the use of any topological regularities in a design such as regular bus structure or the use of the structural property such as the bit-sliceable or non bit-sliceable feature of a module set, or their similar shape. The exploitation of these structural information helps in producing more compact layout especially for datapath oriented architectures. Moreover, in addition to the area and total wiring length, the critical path delay is systematically minimized through a global cost function. The potential candidates for the critical path computation can be specifically defined by the user. The core of the optimization process is based on simulated annealing.<<ETX>>

Synthesis of Multiple Bus Architectures For DSP Applications

In this chapter, we present synthesis techniques of parallel VLSI processor architectures with multiple busses and functional units used for DSP applications. The presented architectures and synthesis approach are most suitable for applications with medium sampling rates (few MSamples/Sec) and medium to large storage requirements (tens to thousands of words) such as in single and multiple channel filtering and transform algorithms. Novel synthesis algorithms and architecture support are described for looped execution of regular algorithms which allow multiple address space for looped variables. These synthesis techniques are used in an architectural synthesis tool “SPAID-X” which inputs the behavior specification as a hierarchical signal flow graph representation that support folded loop constructs. The output of the tool is an architectural specification of the data path and the controller. We demonstrate the functionality of SPAID-X and the quality of the resulting architectures on a number of practical DSP applications and show that it produces results that are favorable to other approaches.

A neural network approach for generating derivative information using quantized robot position measurements

In this paper we propose a generalized methodology for determining first and higher order derivatives of quantized measurements obtained using only position sensors. Our goal is to achieve this objective without use of extra hardware sensors, and at the same time to filter out the noise arising from quantization. We accomplish this using time delay neural networks (TDNN) and compare the performance of this scheme with that obtained using linear filtering techniques. The simulation results show the superiority of the proposed TDNN scheme over the linear filtering approach.<<ETX>>

A two stage structure for high order multi-bit /spl Sigma/-/spl Delta/ ADC with multiplier-less digital correction logic

This paper presents the design methodology of /spl Sigma/-/spl Delta/ ADC that uses a high order single bit first stage, and a multi bit first order second stage and introduces a novel multiplier-less high order digital correction block. The selection of the number of bits and order is done by design graphs that are obtained through numerous simulations under practical tolerances in implementation parameters. By using an example of a 3rd order first stage with a 5-bit second stage, we show that the over-sampling ratio can be reduced to (=<32) while achieving a high bit resolution (>16 bits) for 2% mismatch implementation tolerances between analog and digital parts. Our approach results in an overall increase in the maximum baseband frequency, while the additional digital correction logic is minimal.<<ETX>>