Asim J. Al-Khalili

Performance of Parallel Prefix Adders implemented with FPGA technology

Parallel Prefix Adders have been established as the most efficient circuits for binary addition. Their regular structure and fast performance makes them particularly attractive for VLSI implementation. The classical parallel prefix adder structures that have been proposed over the years optimize for logic depth, area, fan-out and interconnect count of the logic circuits. This paper investigates the performance of parallel prefix adders implemented with FPGA technology. We report on the area requirements and critical path delay for a variety of classical parallel prefix adder structures.

Power estimation tool for sub-micron CMOS VLSI circuits

Accurate and fast time-domain current waveform simulation is important for the design of reliable CMOS VLSI circuits. A detailed current model that resulted in a maximum of 10% deviation from the current waveforms as obtained by SPICE LEVEL 3 at peak values and 5% at the average current is presented. The current model accounts for short-channel effects, input risetimes, short-circuit and dynamic current, and circuit topology. Moreover, the model produces piecewise linear current waveforms and can be incorporated in any switch-level simulator. Using the models in an event driven simulator, a 3-4 orders of magnitude speedup relative to SPICE LEVEL 3 has been achieved. The results for current waveform accuracy are better than those obtained for previously published methods and in particular for complex CMOS circuits.<<ETX>>

Comparison of 32-bit multipliers for various performance measures

Comparison of five different 32-bit integer multipliers is done for various performance measures. Multipliers included in comparison are the array multiplier, modified Booth (radix-4) multiplier, optimized Wallace tree multiplier, combined modified Booth-Wallace tree multiplier and twin pipe serial parallel multiplier. Comparison is based on synthesis results obtained by synthesizing all multiplier architectures towards FPGA.

A low power approach to floating point adder design

We present a new architecture of a low power floating point adder, that is fast and has low latency. The functional partitioning of the adder into three distinct, controlled data paths allows activity reduction. During any given operation cycle, only one of the data paths is active, during which time, the logic assertion status of the circuit nodes of the other data paths are held at their previous states. Critical path delay and latency are reduced by incorporating speculative rounding and pseudo leading zero anticipation logic as well as data path simplifications. The proposed scheme offers a 10/spl times/ reduction in power consumption in comparison to that of conventional high speed floating point adders that use leading zero anticipation logic, for IEEE single precision floating point data format. The reduction in power delay product is about 16/spl times/. The corresponding figures for double precision units are around 40/spl times/ and 66/spl times/ respectively.

A module generator for optimized CMOS buffers

The theory and implementation of a module generator for CMOS buffers are presented. The generator is written in the C language, and outputs optimal buffer designs in respect to a preselected objective function and layout. The user has the choice of minimizing delay, power, and area, or a combination of these, plus the choice of layout configuration. The research concentrates mainly on theoretical analysis, where variations of process, design, and layout parameters with respect to each objective function are studied in detail. >

Urban traffic control — A general approach

An online control policy is presented using hierarchical control theory. It is shown that delays and stops are related to fuel consumption and exhaust emission rate. It is also shown that exhaust emission rate is related to fuel consumption in terms of the control variables cycle time, green time, and the relative offset. A general criterion is presented by which any of the functions of stops, delays, fuel consumption, or exhaust rate emission can be minimized. A complete mathematical description of the control system structure, software, and algorithms of control is given. The algorithms for the control parameters are given mathematically to cover the range of criterion function. All decision sets are evaluated and a procedure for the control policy is described. This online policy has the ability to adjust itself to suit the traffic variation in real time due to its prediction principle and also of selecting the desired function of minimization of stops, delays, fuel consumption, or exhaust emission rate for the whole network or subareas within the network.

Delay analysis of CMOS gates using modified logical effort model

In this paper, modified logical effort (MLE) technique is proposed to provide delay estimation for CMOS gates. The model accounts for the behavior of series-connected MOSFET structure (SCMS), the input transition time, and internodal charges. Also, the model takes into account deep submicron effects, such as mobility degradation and velocity saturation. This model exhibits good accuracy when compared with Spectre simulations based on BSIM3v3 model. Using UMCs 0.13-/spl mu/m and TSMCs 0.18-/spl mu/m technologies, the model has an average error of 4.5% and a maximum error of 15%.

Dual-edge triggered sense amplifier flip-flop for resonant clock distribution networks

A dual-edge sense amplifier flip-flop (DE-SAFF) for resonant clock distribution networks (CDNs) is proposed. The clocking scheme used to enable dual-edge triggering in the proposed SAFF reduces short circuit power by allowing the precharging transistors to be switched on only for a portion of the clock period. The extracted circuit layout of the proposed DE-SAFF has been simulated in STMicroelectronics 90 nm technology with a resonant clock signal at a frequency of 500 MHz. Simulation results show correct functionality of the flip-flip under process, voltage and temperature variations. Two low-power clocking techniques, the dual-edge triggering method and the emerging resonant (sinusoidal) clocking technique, have been combined to enable further power reduction in the CDN. Modelling the resonant clock distribution system with the proposed flip-flop illustrates that dual-edge triggering can achieve up to 58% reduction in the power consumption of resonant clock networks.

Technology-portable analytical model for DSM CMOS inverter transition-time estimation

In this paper, we propose a new analytical model to estimate the transition time of CMOS inverters. Accounting for the main effects of deep sub-micron such as velocity saturation and mobility degradation, the relationship between the input and output transition is discussed and captured by a closed-form expression. The developed model has been formulated to depend only on device model parameters, which are usually provided with the given technology. The proposed model was verified against circuit simulation using Spectre level 11 (BSIM3v3) for a wide range of transistor sizes, output loading and input transition times. It has also been tested for portability between 0.25 /spl mu/m, 0.18 /spl mu/m and 0.13 /spl mu/m technologies Our model showed good accuracy compared to simulation with maximum error of 10% and an average error of 4%.

A Module Generator for Optimized CMOS Buffers

A module generator for CMOS buffers have been written in C. The generator optimizes buffer design with respect to a user specified objective function both in terms of performance and layout. Speed, area, power consumption, power-delay, AT and AT/sup 2/ are selectively optimized before the layout is produced. Such layout is generated in various configurations depending on load size. Technology file is easily updatable.