Bai-Cwo Feng | Researchain

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Publication

Featured researches published by Bai-Cwo Feng.

Archive | 1990

MULTI-LAYER PACKAGE INCORPORATING A RECESSED CAVITY FOR A SEMICONDUCTOR CHIP

Bai-Cwo Feng; George Cheng-Cwo Feng; Richard Henry Mcmaster

Archive | 1976

Planarization of integrated circuit surfaces through selective photoresist masking

Bai-Cwo Feng

Archive | 1978

Two layer resist system

Bai-Cwo Feng; George Cheng-Cwo Feng

Archive | 1976

Forming feedthrough connections for multi-level interconnections metallurgy systems

Bai-Cwo Feng; John S. Lechaton

Archive | 1977

Method of manufacturing self-aligned semiconductor devices

Bai-Cwo Feng; George Cheng-Cwo Feng

Archive | 1978

Process for the fabrication of masks for lithographic processes using a photoresist

Bai-Cwo Feng; George Cheng-Cwo Feng

Archive | 1990

Mehrschichtpackung mit einer vertieften höhlung für einen halbleiter-chip

Bai-Cwo Feng; George Cheng-Cwo Feng; Richard Henry Mcmaster

Archive | 1978

Method of forming very small impurity regions in a semiconductor substrate

Bai-Cwo Feng; George Cheng-Cwo Feng

Archive | 1990

Mehrschichtpackung mit einer vertieften höhlung für einen halbleiter-chip Multilayer packaging with a recessed cavity for a semiconductor chip

Bai-Cwo Feng; George Cheng-Cwo Feng; Richard Henry Mcmaster

Archive | 1978

Verfahren zum Erzeugen von Masken für lithographische Prozesse unter Verwendung von Photolack

Bai-Cwo Feng; George Cheng-Cwo Feng

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George Cheng-Cwo Feng

IBM

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Richard Henry Mcmaster

IBM

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Top Co-Authors

John S. Lechaton

IBM

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Archive Network Publication Hotspot Collaboration

Network

Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot

Dive into the research topics where Bai-Cwo Feng is active.

Publication

Featured researches published by Bai-Cwo Feng.

MULTI-LAYER PACKAGE INCORPORATING A RECESSED CAVITY FOR A SEMICONDUCTOR CHIP

Planarization of integrated circuit surfaces through selective photoresist masking

Two layer resist system

Forming feedthrough connections for multi-level interconnections metallurgy systems

Method of manufacturing self-aligned semiconductor devices

Process for the fabrication of masks for lithographic processes using a photoresist

Mehrschichtpackung mit einer vertieften höhlung für einen halbleiter-chip

Method of forming very small impurity regions in a semiconductor substrate

Mehrschichtpackung mit einer vertieften höhlung für einen halbleiter-chip Multilayer packaging with a recessed cavity for a semiconductor chip

Verfahren zum Erzeugen von Masken für lithographische Prozesse unter Verwendung von Photolack

Collaboration

Dive into the Bai-Cwo Feng's collaboration.