Baijun Zhang

A chip-level electrothermal-coupled design model for high-power light-emitting diodes

An advanced three-dimensional electrothermal-coupled simulation model basing on finite-element method numerical simulation is developed to study the electrical and thermal properties of chip-level high-power GaN-based light-emitting diodes (LEDs). The current spreading, heat generation, and transfer in the device are comprehensively considered in this model. The current-spreading effect of the transparent current-spreading layer and the thermal performance of LEDs with interdigitated-electrodes are investigated. The simulation results prove that the temperature distribution in the active layer is strongly affected by the electrode pattern. The obvious heat accumulation in LEDs with conventional interdigitated-electrode patterns can be seen both in the simulated results and the infrared measured results. The heat transfer efficiency can be improved by using a symmetry electrode pattern design. The thermal management of the bump configurations in flip-chip LEDs is also studied. A more reasonable and thermal...

Enhancement-mode AlGaN/GaN heterostructure field effect transistors fabricated by selective area growth technique

In this letter, a method of using selective area growth (SAG) technique was proposed to fabricate the enhancement-mode (E-mode) AlGaN/GaN heterostructure field effect transistors (HFETs), which can effectively avoid the plasma treatment damage to the active region of HFETs in comparison with the conventional methods. The SAG-HFETs exhibited a good performance of the maximum drain current of 300 mA/mm and peak transconductance of 135 mS/mm with a larger positive threshold voltage of 0.4 V. The results indicate that the SAG technique is a promising method to realize the high performance E-mode GaN based HFETs.

Normally-off GaN recessed-gate MOSFET fabricated by selective area growth technique

In this letter, a normally-off GaN recessed-gate MOSFET is demonstrated using a nonplasma gate recess technique, in which the access region with AlGaN/GaN heterostructure was selectively grown on a semi-insulating GaN/Si template to naturally form a recessed gate. The normally-off recessed-gate Al2O3/GaN MOSFET presents a high threshold voltage of 3.5 V and a maximum drain current density of 550 mA/mm (at a positive gate bias of 12 V). A maximum field-effect mobility of 170 cm2 V−1 s−1 and a large on/off current ratio of more than 107 was obtained, which indicates the high quality of the Al2O3/GaN interface.

Investigations of leakage current properties in semi-insulating GaN grown on Si(1 1 1) substrate with low-temperature AlN interlayers

In this work, the leakage current properties of semi-insulating GaN (SI-GaN) grown on Si(1 1 1) substrate with a low-temperature (LT) AlN interlayer were studied. Two terminal lateral current–voltage measurements revealed an early conduction phenomenon via buffer layers with an LT-AlN interlayer, in which both p- and n-type conduction phenomena were observed from Hall-effect measurement during temperature changing. It is suggested that the p-type conduction existed in the Si substrate due to the diffusion of Al atoms into the Si substrate during the epitaxial growth. The origin of n-type conduction was two-dimensional electron gas (2DEG) in the LT-AlN/GaN interface, which acted as a conduction channel in SI-GaN. Furthermore, the vertical leakage current measurement and the space charge limited current model were used to analyse the impact of the 2DEG conduction channel on the leakage current properties. It is revealed that leakage current properties are very sensitive to the thickness of the GaN layer above the LT-AlN interlayer (Top-GaN). Increasing the thickness of Top-GaN becomes an effective way to suppress leakage current. Therefore, both strain engineering and leakage current properties are essential factors to be considered in the selection of strain compensation interlayer in the growth of SI-GaN on Si substrate for power switching applications.

Vertical-conducting InGaN/GaN multiple quantum wells LEDs with AlN/GaN distributed Bragg reflectors on Si(111) substrate

In this study, crack-free InGaN/GaN multiple quantum well (MQW) LEDs with five-pair AlN/GaN distributed Bragg reflectors (DBRs) were grown on a Si(111) substrate using a linear compositionally graded AlGaN layer to compensate for tensile stresses. DBR-based LEDs exhibited higher light efficiency and better crystalline quality than non-DBR-based LEDs. Vertical-conducting DBR-based LEDs were realized using through-hole structure. Through-holes were formed from the n-GaN layer to the Si substrate and filled with metals, which connected the n-GaN layer and the Si substrate. Insulating AlN, high-resistivity AlGaN layers, and the large band offset at the AlN/Si interface were all shorted by the metal filled into the through-holes. Compared to DBR-based LED without through-holes, DBR-based LEDs with through-holes exhibited significantly better electrical and optical properties.

The suppression of background doping in selective area growth technique for high performance normally-off AlGaN/GaN MOSFET

In this paper, the selective area growth (SAG) technique is used to regrow thin AlGaN/GaN heterostructure on access region for realizing trench gate normally-off AlGaN/GaN MOSFET. Heavy background doping is found in SAG AlGaN/GaN heterostructure, which is not expected for its degradation on device performance. The background doping originates from SiO2 residuals at SAG interface. Through reducing the deposition temperature of SiO2 mask, background doping can be efficiently suppressed. As a result, the 2 dimensional electron gas transport property of SAG AlGaN/GaN heterostructure improves greatly, which is as good as the as-grown AlGaN/GaN heterostructure. Moreover, the performance of normally-off SAG AlGaN/GaN MOSFET improves greatly by suppression the Si residual on GaN template.

Selective Area Growth: A Promising Way for Recessed Gate GaN MOSFET With High Quality MOS Interface

Based on the selective area growth (SAG) technique, an enhancement mode GaN recessed gate MOSFET was fabricated successfully with negligible gate trapping effect, presenting an extremely small threshold voltage (Vth) hysteresis of 50 mV at a gate bias swing up to 10 V. Compared with the larger Vth hysteresis of a recessed gate GaN MOSFET fabricated by dry-etching, the correlation between the Vth hysteresis and the lattice damage related traps caused by plasma dry etching process has been confirmed. Furthermore, the SAG recessed MOSFET shows a lower turn-ON resistance due to the higher MOS channel mobility. We believe that all of these superior performance of SAG MOSFET are attributed to the damage free high quality GaN surface at the Al2O3/GaN MOS interface, which indicates that the SAG is a promising alternative technique toward stable GaN MOSFET for the power switching applications.

Improving the Quality of GaN on Si(111) Substrate with a Medium-Temperature/High-Temperature Bilayer AlN Buffer

A medium-temperature/high-temperature (MT/HT) bilayer AlN buffer was introduced for GaN grown on Si(111) by metal organic chemical vapor deposition. The properties of the GaN films with a MT/HT bilayer AlN buffer and those with a single-layer HT-AlN buffer were compared and the influence of the growth temperature of the MT-AlN layer was investigated. With a MT-AlN layer grown in the temperature range from 800 to 1000 °C, the crystalline qualities of the subsequent HT-AlN layer and the GaN film were improved. According to the X-ray diffraction results and the transmission electron microscopy images, the dislocation density in GaN film was reduced with a MT/HT bilayer AlN buffer as compared to those with a single-layer HT-AlN buffer. Moreover, photoluminescence and Raman spectra exhibit enhanced optical properties and less tensile stresses of the GaN film. Better surface morphology of GaN was also obtained with a MT/HT bilayer AlN buffer.

Optical properties of ZnO/MgZnO quantum wells with graded thickness

National Natural Science Foundation of China [60876007, 10974165]; State Key Laboratory of Optoelectronic Materials and Technologies (Sun Yat-sen University) [KF2010-ZD-08]

Influence of the carbon-doping location on the material and electrical properties of a AlGaN/GaN heterostructure on Si substrate

The influence of different C-doping locations in a GaN/Si structure with a GaN/AlN superlattice (SL) buffer on the material and electrical properties of GaN/Si was studied. The introduction of C doping can remarkably degrade the crystal quality of the buffer. C-doping of a top GaN buffer can introduce compressive stress into the top GaN due to the size effect, while C-doping in a SL buffer can impair the compressive stress provided from the SL buffer to the top GaN. It is found that introducing high-density carbon into the whole buffer can result in a more strain-balanced GaN/Si system with small deterioration of the 2DEG channel. Furthermore, the whole buffer C-doping method is an effective and easy way to achieve a thin buffer with low leakage current and high breakdown voltage (266 V@1 nA mm−1; 698 V@10 μA mm−1; 912 V@1 mA mm−1). By using the whole-buffer C-doping method, a 2.5 μm-thick AlGaN/GaN HFET with a breakdown voltage higher than 900 V was achieved, and the breakdown voltage per unit buffer thickness can reach 181 V μm−1.