Yiqiang Ni

Normally-off GaN recessed-gate MOSFET fabricated by selective area growth technique

In this letter, a normally-off GaN recessed-gate MOSFET is demonstrated using a nonplasma gate recess technique, in which the access region with AlGaN/GaN heterostructure was selectively grown on a semi-insulating GaN/Si template to naturally form a recessed gate. The normally-off recessed-gate Al2O3/GaN MOSFET presents a high threshold voltage of 3.5 V and a maximum drain current density of 550 mA/mm (at a positive gate bias of 12 V). A maximum field-effect mobility of 170 cm2 V−1 s−1 and a large on/off current ratio of more than 107 was obtained, which indicates the high quality of the Al2O3/GaN interface.

Investigations of leakage current properties in semi-insulating GaN grown on Si(1 1 1) substrate with low-temperature AlN interlayers

In this work, the leakage current properties of semi-insulating GaN (SI-GaN) grown on Si(1 1 1) substrate with a low-temperature (LT) AlN interlayer were studied. Two terminal lateral current–voltage measurements revealed an early conduction phenomenon via buffer layers with an LT-AlN interlayer, in which both p- and n-type conduction phenomena were observed from Hall-effect measurement during temperature changing. It is suggested that the p-type conduction existed in the Si substrate due to the diffusion of Al atoms into the Si substrate during the epitaxial growth. The origin of n-type conduction was two-dimensional electron gas (2DEG) in the LT-AlN/GaN interface, which acted as a conduction channel in SI-GaN. Furthermore, the vertical leakage current measurement and the space charge limited current model were used to analyse the impact of the 2DEG conduction channel on the leakage current properties. It is revealed that leakage current properties are very sensitive to the thickness of the GaN layer above the LT-AlN interlayer (Top-GaN). Increasing the thickness of Top-GaN becomes an effective way to suppress leakage current. Therefore, both strain engineering and leakage current properties are essential factors to be considered in the selection of strain compensation interlayer in the growth of SI-GaN on Si substrate for power switching applications.

Effect of AlN/GaN superlattice buffer on the strain state in GaN-on-Si(111) system

The effect of AlN/GaN superlattice (SL) buffer on the strain state in a GaN-on-Si(111) system was studied in detail by room-temperature micro-Raman scattering measurement. An abnormal satellite peak attached to a GaN E2 peak was observed, which was verified to stem from the compressively strained GaN in SLs. The results indicate that the strain-sensitive GaN E2 (high) peak in the GaN-on-Si system with AlN/GaN SLs splits into two peaks because the GaN stress state in the top GaN layer is different from that in SLs. The compressive stress in the GaN layer in SLs was introduced by the AlN layer in each SL period because of the lattice mismatch between GaN and AlN, which ultimately counterbalanced the tensile stress in the top GaN during cooling. Such a counterbalance interaction is strongly dependent on the stiffness coefficient of AlN/GaN SLs, which is proportional to the number of periods of SLs and the relative thickness of AlN in SLs. Such two E2 peaks from GaN enable us to monitor the strain state in the GaN-on-Si system with AlN/GaN SLs quantitatively.

Current transport mechanism of AlGaN/GaN Schottky barrier diode with fully recessed Schottky anode

Both the forward and reverse-bias current transport mechanisms of an AlGaN/GaN Schottky barrier diode with a fully recessed Schottky anode (recessed-SBD) are investigated for the first time. A two-dimensional (2D) device simulation gives insight into the electronic transport. The difference between the forward and reverse conduction paths enables the reduction in Von without sacrificing the low reverse leakage current properties. The results of temperature-dependent current–voltage (T–I–V) measurements show that thermionic field emission (TFE) is the dominant current transport mechanism for forward bias. In the reverse-bias region above the pinch-off voltage, two mechanisms codetermine leakage currents, which contain Frenkel–Poole emission from the overlapped planar contact and tunneling from the recessed sidewall contact. Below the pinch-off voltage, the leakage currents are observed to have exponential temperature dependence, which may be consistent with trap-assisted tunneling (TAT).

The suppression of background doping in selective area growth technique for high performance normally-off AlGaN/GaN MOSFET

In this paper, the selective area growth (SAG) technique is used to regrow thin AlGaN/GaN heterostructure on access region for realizing trench gate normally-off AlGaN/GaN MOSFET. Heavy background doping is found in SAG AlGaN/GaN heterostructure, which is not expected for its degradation on device performance. The background doping originates from SiO2 residuals at SAG interface. Through reducing the deposition temperature of SiO2 mask, background doping can be efficiently suppressed. As a result, the 2 dimensional electron gas transport property of SAG AlGaN/GaN heterostructure improves greatly, which is as good as the as-grown AlGaN/GaN heterostructure. Moreover, the performance of normally-off SAG AlGaN/GaN MOSFET improves greatly by suppression the Si residual on GaN template.

Selective Area Growth: A Promising Way for Recessed Gate GaN MOSFET With High Quality MOS Interface

Based on the selective area growth (SAG) technique, an enhancement mode GaN recessed gate MOSFET was fabricated successfully with negligible gate trapping effect, presenting an extremely small threshold voltage (Vth) hysteresis of 50 mV at a gate bias swing up to 10 V. Compared with the larger Vth hysteresis of a recessed gate GaN MOSFET fabricated by dry-etching, the correlation between the Vth hysteresis and the lattice damage related traps caused by plasma dry etching process has been confirmed. Furthermore, the SAG recessed MOSFET shows a lower turn-ON resistance due to the higher MOS channel mobility. We believe that all of these superior performance of SAG MOSFET are attributed to the damage free high quality GaN surface at the Al2O3/GaN MOS interface, which indicates that the SAG is a promising alternative technique toward stable GaN MOSFET for the power switching applications.

Comparison of Two Types of Recessed-Gate Normally-Off AlGaN/GaN Heterostructure Field Effect Transistors

In this report, two types of normally-off AlGaN/GaN heterostructure field effect transistors (HFETs) with recessed-gate structure have been fabricated by using common technique of induced coupled plasma (ICP) dry etching and a novel technique of selective area growth (SAG), respectively. The devices fabricated by SAG (SAG-HFET) showed better performance than that of ICP-HFETs with larger maximum drain current of 300 mA/mm, positive threshold voltage of 0.4 V, and lower pinch off channel leakage current (2.17×10-3 mA/mm). The analysis indicates that such obvious difference originated from the different AlGaN quality of the gate region under the Schottky contact, in which the damage to the gate region stemmed from dry etching can be avoided by the SAG technique so that the forming of higher quality Schottky contact can be guaranteed. These results indicate that SAG technique is a promising method for fabricating the normally-off GaN based HFETs.

Influence of the carbon-doping location on the material and electrical properties of a AlGaN/GaN heterostructure on Si substrate

The influence of different C-doping locations in a GaN/Si structure with a GaN/AlN superlattice (SL) buffer on the material and electrical properties of GaN/Si was studied. The introduction of C doping can remarkably degrade the crystal quality of the buffer. C-doping of a top GaN buffer can introduce compressive stress into the top GaN due to the size effect, while C-doping in a SL buffer can impair the compressive stress provided from the SL buffer to the top GaN. It is found that introducing high-density carbon into the whole buffer can result in a more strain-balanced GaN/Si system with small deterioration of the 2DEG channel. Furthermore, the whole buffer C-doping method is an effective and easy way to achieve a thin buffer with low leakage current and high breakdown voltage (266 V@1 nA mm−1; 698 V@10 μA mm−1; 912 V@1 mA mm−1). By using the whole-buffer C-doping method, a 2.5 μm-thick AlGaN/GaN HFET with a breakdown voltage higher than 900 V was achieved, and the breakdown voltage per unit buffer thickness can reach 181 V μm−1.

Influence of the Aln/Gan superlattices buffer thickness on the electrical properties of Algan/Gan HFET on Si substrate

The influence of the total thickness (periods of AlN/GaN SLs) of AlN/GaN superlattices (SLs) buffer on the static electrical properties of AlGaN/GaN HFETs is study for the purpose of improving devices breakdown voltage (BV) and reducing its on-resistance (R<inf>ON</inf>). It is found that for top-GaN layer with a constant thickness of lμm, a proper thickness of AlN/GaN SLs buffer (such as 2.5 μm with 100 period AlN/GaN SLs) could obtain better crystal quality of top-GaN layer as well as more robust devices with more superior performance in all aspects. The most robust HFETs in this work have achieved a specific on-resistance (R<inf>ON, SP</inf>) of 0.68 mΩ-cm² (@ L<inf>GD</inf>=4μm), a maximum on-state drain current (I<inf>D, max</inf>) of 430 mA/mm (@ L<inf>GD</inf>=4μm), an On/Off ratio of 2×10⁸, a BV of 552V at a drain leakage current of lμA/mm (@ L<inf>GD</inf>=15μm), and a figure-of-merit (FOM=BV²/R<inf>ON, SP</inf>) of 168 MW/cm² (@ L<inf>GD</inf>=8μm).

A novel normally-off GaN MISFET with an in-situ AlN space layer using selective area growth

In this paper, we present a recessed-gate normally-off Al₂O₃/AlN/GaN MISFET with stable threshold voltage based on selective area growth (SAG) of AlGaN/GaN heterostructure on AlN/GaN/Si template. By in-situ growth of a thin AlN space layer (SL) in MOCVD, GaO_x can be blocked fundamentally and a high-quality Al₂O₃/AlN/GaN interface is achieved. Thus, the device exhibits a comprehensive upgrade performance with a low threshold voltage hysteresis (ΔV_th) of 75 mV at V_g=10 V, a high peak field-effect mobility (μ_FE) of 187 cm²/V-s, a maximum drain current of 620 mA/mm and an improved frequency dispersion.