Baker Mohammad

Characterization of Human Body-Based Thermal and Vibration Energy Harvesting for Wearable Devices

Energy harvesting is an important enabling technology necessary to unleash the next shift in mm-scale and μW power computing devices, especially for wireless sensor nodes. Energy harvesting could play an important role in biomedical devices where it extends the lifetime of the system. Furthermore, it eliminates the need for periodic maintenance such as exchanging or recharging the battery. This paper presents experimental results of thermal and vibration energy harvested from human body using the thermoelectric generator and the piezo electric harvester, respectively. Contemporary research revealed that most of the published data, including harvesters datasheets, are adjusted for industrial or laboratory-setting environment. This paper focuses on obtaining experimental data from the human body using off-the-shelf harvesters, and discrete electrical components. Our experimental results showed that for 9 cm 2 area of thermoelectric generator, up to 20 μW of power can be generated at 22 °C room temperature. In addition, 0.5 cm 3 piezo electric harvester can generate up to 3.7 μW when running at 7 mi/h. These data correspond to a power density of 2.2 μW/cm 2 and 7.4 μW/cm 3 for thermoelectric generator and piezo electric harvester, respectively. As such, the harvested energy from thermal and vibration of human body could potentially power autonomous wearable and implantable devices.

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

This paper presents the design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricular arrhythmia using a unique set of ECG features and a naive Bayes classifier. Real-time and adaptive techniques for the detection and the delineation of the P-QRS-T waves were investigated to extract the fiducial points. Those techniques are robust to any variations in the ECG signal with high sensitivity and precision. Two databases of the heart signal recordings from the MIT PhysioNet and the American Heart Association were used as a validation set to evaluate the performance of the processor. Based on application-specified integrated circuit (ASIC) simulation results, the overall classification accuracy was found to be 86% on the out-of-sample validation data with 3-s window size. The architecture of the proposed ESP was implemented using 65-nm CMOS process. It occupied 0.112-mm2 area and consumed 2.78-μW power at an operating frequency of 10 kHz and from an operating voltage of 1 V. It is worth mentioning that the proposed ESP is the first ASIC implementation of an ECG-based processor that is used for the prediction of ventricular arrhythmia up to 3 h before the onset.

Robust Hybrid Memristor-CMOS Memory: Modeling and Design

In this paper, we explore various aspects of memristor modeling and use them to propose improved access operations and design of a memristor-based memory. We study the current mathematical and SPICE modeling of memristors and compare them with known device specifications. Based on this survey of existing models, we adopt an improved mathematical model of the memristor that captures the well-established features of memristive devices. This modeling is used to analyze the time and voltage characteristics of stable read and write operations. The tradeoffs between the various design parameters such as voltage, frequency, noise margin, and area are also analyzed. Based on the device modeling, we propose a hybrid CMOS-memristor memory cell and architecture that addresses the limitations of memristor such as state drift, cell-cell interference, and refresh requirements. Memristor is used as a state element, and CMOS-based transistors are used to isolate, control, decode, and inter operate the logic. We verify our design using SPICE simulation using a 28-nm model for CMOS and a modified memristor model.

Cache Design for Low Power and High Yield

A novel circuit approach to increase SRAM static noise margin (SNM) and enable lower operating voltage is described. Increasing process variability [1] [2] for new technologies coupled with increased reliability effects like negative bias temperature instability (NBTI) [3] all contribute to raising the minimum voltage required for stable SRAM. Our strategy is to improve the noise margin of the 6T SRAM cell by reducing the effect of parametric variation of the cell [4], especially in the low voltage operation mode. This is done using a novel circuit that selectively reduces the voltage swing on the world line and reduces the memory supply voltage during write operation. The proposed design increases the SRAM static noise margin (SNM) and write margin using a single voltage supply and with minimum impact to chip area, complexity, and timing. The technique supports both on-chip corner identification to adapt the SRAM behavior to silicon, and software controllability to tradeoff yield, power, and performance.

State of the art of metal oxide memristor devices

Abstract Memristors are one of the emerging technologies that can potentially replace state-of-the-art integrated electronic devices for advanced computing and digital and analog circuit applications including neuromorphic networks. Over the past few years, research and development mostly focused on revolutionizing the metal oxide materials, which are used as core components of the popular metal-insulator-metal memristors owing to their highly recognized resistive switching behavior. This paper outlines the recent advancements and characteristics of such memristive devices, with a special focus on (i) their established resistive switching mechanisms and (ii) the key challenges associated with their fabrication processes including the impeding criteria of material adaptation for the electrode, capping, and insulator component layers. Potential applications and an outlook into future development of metal oxide memristive devices are also outlined.

Mathematical modeling of a memristor device

The realization of the missing fourth element by Hewlett-Packard in 2008, the memristor, adds new promising technology that enables the continuing improvement of performance, power and cost of integrated circuits and keeping Moores law alive. Memristor-based technology provides much better scalability, higher utilization when used as memory, and overall lower power consumption. This paper presents a detailed study of existing memristor modeling using Matlab simulations. We studied three different models to predict the behavior of the memristor device. We developed the Matlab algorithms for all models and analyzed them for their compatibility with the experimentally established characteristics of HP memristor, as well as their viability for use in memory circuits. We discussed all the difficulties with these models and adopt a modified model that gives more realistic description of a memristor device.

Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications

Conventional charge-based memory usage in low-power applications is facing major challenges. Some of these challenges are leakage current for static random access memory (SRAM) and dynamic random access memory (DRAM), additional refresh operation for DRAM, and high programming voltage for Flash. In this paper, two emerging resistive random access memory (ReRAM) technologies are investigated, memristor and spin-transfer torque (STT)-RAM, as potential universal memory candidates to replace traditional ones. Both of these nonvolatile memories support zero leakage and low-voltage operation during read access, which makes them ideal for devices with long sleep time. To date, high write energy for both memristor and STT-RAM is one of the major inhibitors for adopting the technologies. The primary contribution of this paper is centered on addressing the high write energy issue by trading off retention time with noise margin. In doing so, the memristor and STT-RAM power has been compared with the traditional six-transistor-SRAM-based memory power and potential application in wireless sensor nodes is explored. This paper uses 45-nm foundry process technology data for SRAM and physics-based mathematical models derived from real devices for memristor and STT-RAM. The simulations are conducted using MATLAB and the results show a potential power savings of 87% and 77% when using memristor and STT-RAM, respectively, at 1% duty cycle.

Adaptive technique for P and T wave delineation in electrocardiogram signals.

The T and P waves of electrocardiogram signals are excellent indicators in the analysis and interpretation of cardiac arrhythmia. As such, the need to address and develop an accurate delineation technique for the detection of these waves is necessary. In this paper, we present a novel robust and adaptive T and P wave delineation method for real-time analysis and nonstandard ECG morphologies. The proposed method is based on ECG signal filtering, value estimation of different fiducial points, applying backward and forward search windows as well as adaptive thresholds. Simulations and evaluations prove the accuracy of the proposed technique in comparison to those proposed techniques in the literature. The mean error for the T peak, T offset, P peak and P offset values are found to be 9.8, 2.3, 7.3 and 3.5 milliseconds, respectively, based on the Physionet QT database, rendering our algorithm as an excellent candidate for ECG signal analysis.

10.1 A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications

A very-long instruction word (VLIW) Hexagon™ DSP is fabricated using a 28 nm high-κ metal-gate process technology optimized for mobile applications [1]. The DSP is designed for a heterogeneous computing environment. It targets high performance and low power across a wide variety of multimedia and modem applications, under aggressive area targets. Its architecture pursues high IPC as opposed to high frequency [2]. It includes a 32 kB L1 data cache (D

A survey of thermal energy harvesting techniques and interface circuitry

), a 16 kB L1 instruction cache (I