Temesghen Tekeste

Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia

This paper presents the design of a fully integrated electrocardiogram (ECG) signal processor (ESP) for the prediction of ventricular arrhythmia using a unique set of ECG features and a naive Bayes classifier. Real-time and adaptive techniques for the detection and the delineation of the P-QRS-T waves were investigated to extract the fiducial points. Those techniques are robust to any variations in the ECG signal with high sensitivity and precision. Two databases of the heart signal recordings from the MIT PhysioNet and the American Heart Association were used as a validation set to evaluate the performance of the processor. Based on application-specified integrated circuit (ASIC) simulation results, the overall classification accuracy was found to be 86% on the out-of-sample validation data with 3-s window size. The architecture of the proposed ESP was implemented using 65-nm CMOS process. It occupied 0.112-mm2 area and consumed 2.78-μW power at an operating frequency of 10 kHz and from an operating voltage of 1 V. It is worth mentioning that the proposed ESP is the first ASIC implementation of an ECG-based processor that is used for the prediction of ventricular arrhythmia up to 3 h before the onset.

Adaptive technique for P and T wave delineation in electrocardiogram signals.

The T and P waves of electrocardiogram signals are excellent indicators in the analysis and interpretation of cardiac arrhythmia. As such, the need to address and develop an accurate delineation technique for the detection of these waves is necessary. In this paper, we present a novel robust and adaptive T and P wave delineation method for real-time analysis and nonstandard ECG morphologies. The proposed method is based on ECG signal filtering, value estimation of different fiducial points, applying backward and forward search windows as well as adaptive thresholds. Simulations and evaluations prove the accuracy of the proposed technique in comparison to those proposed techniques in the literature. The mean error for the T peak, T offset, P peak and P offset values are found to be 9.8, 2.3, 7.3 and 3.5 milliseconds, respectively, based on the Physionet QT database, rendering our algorithm as an excellent candidate for ECG signal analysis.

Adaptive ECG interval extraction

ECG intervals such as QRS, QT and PR provide significant information and are widely used as clinical parameters for diagnosing cardiac diseases. This paper presents a novel QRS detection technique based on Curve Length Transform (CLT) and a refined delineation of P-wave and T-wave using Discrete Wavelet Transform (DWT). The proposed technique was verified using the PhysioNet database. The QRS detection achieved a sensitivity of 98.59% and a positive predictivity of 97.86%. The QRS duration, QT interval and PR interval had a mean error of -1.56± 28.8ms, -5.39± 42.4ms and 0.86± 40.3ms respectively. The proposed algorithm is computationally efficient and is simpler to implement in hardware, hence, will lead to a faster execution time, smaller design area and consequently low power consumption.

Ultra-Low Power, Secure IoT Platform for Predicting Cardiovascular Diseases

Internet of Things (IoT) promises to revolutionize the health-care sector through remote, continuous, and non-invasive monitoring of patients. However, there are two main challenges faced by the IoT-enabled medical devices: energy-efficiency and security/privacy concerns. Researchers have independently attempted to develop solutions, such as low-power ECG-processors and security protocols, that address these challenges on an individual basis. However, it is imperative to investigate holistic solutions that integrate in a synergistic manner, delivering an overall secure and energy-efficient product. In this paper, we develop an ultra-low power and secure IoT sensing/pre-processing platform for prediction of ventricular arrhythmia using ECG signals. Our proposed solution is able to predict the on-set of the critical cardiovascular events upto 3 h in advance with 86% accuracy. Moreover, the proposed architecture is designed using an Application Specific Integrated Circuits design flow in 65-nm Low Power Enhanced technology; the power it consumes is 62.2% less than that of the state-of-the-art approaches, while occupying 16.0% smaller area. The proposed processor makes use of ECG signals to extract a chip-specific ECG key that enables protection of communication channel. By integrating the ECG key with an existing design-for-trust solution, the proposed platform offers protection also at the hardware level, thwarting hardware security threats, such as reverse engineering and counterfeiting. Through efficient sharing of on-chip resources, the overhead of the multi-layered security infrastructure is kept at 9.5% for area and 0.7% for power with no impact on the speed of the design.

A biomedical SoC architecture for predicting ventricular arrhythmia

Electrocardiography (ECG) represents the hearts electrical activity and has features such as QRS complex, P-wave and T-wave that provide critical clinical information for detection and prediction of cardiac diseases. This paper presents a novel ECG processing architecture for the prediction of ventricular arrhythmia (VA). The architecture implements a novel ECG feature extraction which is optimized for ultra-low power applications. The architecture is based on Curve Length Transform (CLT) for the detection of QRS complex and Discrete Wavelet Transform (DWT) for the delineation of TP waves. Features extracted from two consecutive ECG cycles are used to set innovative parameters for VA prediction up to 3 hours before VA onset. Two databases of the heart signal recordings from the American Heart Association (AHA) and the MIT PhysioNet were used as training, test and validation sets to evaluate the performance of the proposed system.

A 65-nm low power ECG feature extraction system

This paper presents a real-time adaptive ECG detection and delineation algorithm alongside an architecture based on time-domain signal processing of the ECG signal. The algorithm is enhanced to detect large number of different P-QRS-T waveform morphologies using adaptive search windows and adaptive threshold levels. The proposed architecture has been implemented in the state-of-the-art 65-nm CMOS technology. It occupied 0.03416 mm2 area and consumed 0.614 mW power. Furthermore, the non-complex nature of the architecture resulted with a realization using smaller number of computation and higher performance. The design of the QRS detector was tested on ECG records obtained from the Physionet QT database and achieved a sensitivity of Se =99.83% and a positive predictivity of P+= 98.65%. Similarly, the mean error values of the T peak, T offset, P peak and P offset were found to be -1.367, 6.36, 5.5 and -2.59 milliseconds, respectively, using the same database. The small area, low power, and high performance of our architecture makes it suitable for inclusion in System On Chips (SOCs) targeting wearable mobile medical devices.

Power management unit for multi-source energy harvesting in wearable electronics

This paper presents a power management unit (PMU) architecture for multi-source energy harvesting system in wearable devices. The energy harvesting system utilizes a thermal and vibration harvesters as energy sources. In addition, the PMU is designed to control the harvested energy as well as to manage the power delivered to an ECG processor. Further, the PMU generates different signals to enable and disable the processor depending on the available energy. The ECG processor analyzes ECG signals and predicts ventricular arrhythmia (VA). The ECG processor is a multi-voltage design that uses a 0.6V for the processing core and a 1V for the SRAM. Simulation results of the PMU shows the operation of the ECG processor at different energy states in different modes of operation. The proposed architecture could help wearable electronics to run at their optimum energy point to increase their life time.

Ultra-Low-Power ECG Processor for IoT SOCs

This chapter presents an ultra-low-power ECG processor for applications of IoT devices. It includes full system description consisting of ECG analog front end, ECG feature extraction and ventricular arrhythmia (VA) prediction system. Each of these components operate at ultra-low-power dissipation utilizing low-power circuits and architectures. The digital processing part is computation efficient that does ECG feature extraction using curve length transform (CLT) and discrete wavelet transform (DWT) . Moreover, the VA predictor is implemented using linear classifier which is also hardware friendly.

Efficient Algorithm for VT/VF Prediction for IoT SoCs

In this chapter, a novel algorithm for predicting ventricular arrhythmia (VA) is presented. It utilizes a unique set of ECG features with LDA classifier. These features are extracted from two consecutive heartbeats. The proposed method achieves a capability of predicting the arrhythmia up to 3 h before the onset with an accuracy of 99.1\(\%\) sensitivity of 98.95\(\%\) and precision of 98.39\(\%\).

Fused floating point arithmetic for discrete wavelet transform

Floating point arithmetic provides high resolution and wide range for representing numbers. However it requires huge resources and high power consumption which makes it unfavorable for implementation in power constrained wearable devices. In this paper we present fused floating point arithmetic for realizing Discrete Wavelet Transform (DWT). Comparative analysis is performed to determine the advantages of fused floating point. Implementing DWT using fused floating point dot product required 22% less area than using conventional floating point arithmetic. Moreover the required power consumption is 67% less. DWT is chosen in the analysis since it is widely used in wearable ECG processors due to its inherent behavior to suppress noise.