Balal Ahmad

Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC

This paper describes the architecture of our dynamically reconfigurable network-on-chip (NoC) architecture that has been proposed for reconfigurable multiprocessor system-on-chip (MPSoC), as a solution to the increased communication needs, low silicon cost, quality of service and scalability of network in mind. The novelty of the proposed NoC lies in the fact that it dynamically configures itself with respect to routing, switching and data packet size with the changing communication requirements of the system at run time, thus aiming to provide low latency, low power and high data throughput. Simulation results and a prototype implementation of the idea have shown its efficiency when simulated under different traffic condition at a negligible area overhead

Dynamically Reconfigurable NoC with Bus Based Interface for Ease of Integration and Reduced Design Time

This paper demonstrates our implementation of a dynamically reconfigurable network on chip router with bus based interface. Our work targets heterogeneous integration of components in NoC architecture and includes modeling of reconfigurable components, processor cores and fixed IPs. The novelty of the proposed NoC lies in its ability to integrate standard non-packet based components thus reducing design time and ease of integration. A system consisting of an ARM processor, reconfigurable FFT, reconfigurable Viterbi decoder, memory controller and peripherals is considered with the option of system scalability for future upgrades. A framework for system level modeling of reconfigurable NoC with reconfigurable components is also proposed and demonstrated in systemC. Results are compared with implementation of the same system with conventional NoC to demonstrate advantages of the proposed NoC architecture.

System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design

In the system-on-chip (SoC) era, the growing number of functionalities included on a single chip requires the development of new design methodologies to keep the design complexity under control. Intellectual property reuse has been commonly employed as a technique to address this problem, but a new system-level approach is needed to integrate IP-Reuse methodology in the design flow, in order to speed up the designers productivity. This paper aims to produce new high level IP models in SystemC for functional verification of IP integrations, incorporating both embedded custom reconfigurable and conventional IPs, which are optimised in terms of IP Core parameters. As a case study, a novel reconfigurable FFT architecture is presented and modelled in SystemC. Power, area and performance figures are presented as well.

Dynamically reconfigurable NoC for reconfigurable MPSoC

The performance of a multiprocessor system-on-chip (MPSoC) is not only dependent on the computational capabilities of on-chip processors but also depends on the communication medium connecting them. This has shifted the emphasis from computation to communication architectural design. In this paper, a dynamically reconfigurable network-on-chip (NoC) architecture has been proposed for reconfigurable MPSoC, as a solution to the increased communication needs, keeping low power, quality of service (QoS) and scalability of network in mind

Efficient High-Level Power Estimation for Multi-standard Wireless Systems

This paper aims at providing a new system level power estimation methodology based on transaction level modelling (SystemC) for wireless applications, which can highly improve the trade-off between accuracy and efficiency of power estimation in system level. The main features of our novel simulation environment for SystemC will be presented, which allows the easy introduction of a power model in the executable specification of a sophisticated wireless design. It allows efficient power estimation of reconfigurable cores by state based power modelling, which leads to a viable solution for early power aware design of multi-standard wireless systems. The simulator has been applied to the SystemC modules of a WiMAX receiver based on ARM processor, reconfigurable FFT and Viterbi, and AMBA bus. The power figures have been compared with the results obtained from industrial tools.

SystemC-based Reconfigurable IP Modelling for System-on-Chip Design

A new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designersA new system-level approach is needed to incorporate reconfigurability in IP-inegration design flow, in order to speed up the designers productivity. SystemC is used as a system level language to raise the abstraction level for embedded systems design and verification. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different run-time periods. Co-simulation scenario is proposed as a part of a system-on-chip (SoC) design and modelling. SystemC-HDL co-simulation scenario provides a way of checking interoperability of a single designed HW module with the SystemC model. As a case study, novel reconfigurable FFT and Viterbi architectures are modelled in SystemC, and plugged into a LEON platform for co-simulation. productivity. SystemC is used as a system level language to raise the abstraction level for embedded systems design and verification. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different run-time periods. Co-simulation scenario is proposed as a part of a system-on-chip (SoC) design and modelling. SystemC-HDL co-simulation scenario provides a way of checking interoperability of a single designed HW module with the SystemC model. As a case study, novel reconfigurable FFT and Viterbi architectures are modelled in SystemC, and plugged into a LEON platform for co-simulation.

System-Level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems

A new system-level approach is needed to incorporate re-configurability in IP-integration design flow, in order to speed up the designers productivity. To incorporate reconfiguration aspects of IPs, a multiple-context representation of the different functionalities is used that will be mapped on the re-configurable block during different run-time periods. Co-simulation scenario is proposed as a part of a system-on-chip (SoC) design and modelling. SystemC-HDL co-simulation scenario provides a way of checking interoperability of a single designed HW module with the SystemC model. As a case study, novel reconfigurable FFT and Viterbi architectures are modelled in SystemC, and co-simulated in a C-based WiMAX system. Area and power consumption of main blocks in WiMAX are analysed.

A state based framework for efficient system-level power estimation of of costum reconfigurable cores

This paper presents a new system level power estimation methodology based on transaction level modeling for costum reconfigurable cores. The methodology can lead to significant improvement in trade-off between accuracy and efficiency of power estimation at system level. A SystemC based simulation environment is presented that allows rapid introduction of a power model into the executable specification of a sophisticated reconfigurable hardware design. The proposed environment allows efficient power estimation of custom reconfigurable cores through state based power modeling, leading to a viable solution for early power aware design. The simulator has been applied to SystemC module of a custom reconfigurable core for Viterbi decoding. Power figures have been compared with the results obtained by state of the art industrial tools.

Communication Centric Modelling of System on Chip Devices Targeting Multi-standard Telecommunication Applications

In this paper we propose a novel framework for modelling heterogeneous SoC architectures with emphasis on reconfigurable component integration and optimised communication media. Our work targets three major issues faced by the current SoC design methodologies; a novel hybrid communication topology, communication centric platforms and modelling of reconfigurable components in the system. Multi-standard telecommunication applications are chosen as our target domain and a case study of WiMAX is used as a real world example to demonstrate the novelty of our work. A system consisting of an ARM processor, reconfigurable FFT and reconfigurable Viterbi decoder is considered with the option of system scalability for future upgrades. Behaviour of system with different communication platforms is analysed for its throughput and power characteristics with different reconfigurable scenarios to show the effectiveness of our approach.