Baoliang Li

An Improved Wireless Sensor Networks Routing Protocol Based on AODV

We propose an improved protocol based on Ad hoc On-Demand Distance Vector Routing (AODV) to adapt to the features such as energy limited and frequent topology changes in Wireless Sensor Networks (WSN). Based on the residual energy and communication load of each node, this protocol creates some routes from the source node to destination node, and then chooses a route to send data packets according to their reliability. When the route breaks up caused by the nodes mobility or running out of energy, this protocol will choose a backup node which has a strong communication capability to forward data packets according to the backup routings information. The simulation results on OMNET++ shows that this protocol has a good performance on network life cycle, latency, packet transmission rate and so on.

A Highly Scalable Butterfly-Based Photonic Network-on-Chip

Future chip multiprocessors will requires low-power, high performance on-chip networks. Photonic interconnects is a promising way to leverage silicon photonics for future CMPs. In this paper, we present a highly scalable BPNoC(butterfly-based photonic NoC). The most important feature of our proposed network is that it can scale to a more large size with acceptable performance by utilizing the characteristics of butterfly topology and basic photonic switching element (PSE2x2). BPNoC is a hierarchical network with an optical sub-network and an electrical sub-network. Optical sub-network with a load-balanced routing algorithm use circuit-based switching to transmit data packets, while the electronic sub-network with improved turn-around algorithm is based on packet-switching for control and data packet transmission. Finally, we analyze the optical loss, power consumption, and network performance for 64-core BPNoC under various synthetic traffic patterns. The results show that our proposed network has much low optical loss, good performance, and high energy efficiency.

Designing Voltage-Frequency Island Aware Power-Efficient NoC through Slack Optimization

In network-on-chips (NoCs), power consumption has become the main design constraint. In this paper, we propose a power-efficient network calculus-based (PNC) method to minimize the power consumption of NoC. Based on the slack that a packet can be further delayed in the network without violating its deadline, Our PNC method uses power-gating technique to reduce the active buffer size and uses voltage-frequency scaling technique to reduce the voltage-frequency of each voltage-frequency island. With less active buffer units and lower voltage- frequency, the power consumption of NoC is reduced. Experimental results show that our PNC method can save at most 50% of the total power consumption.

An independent but not identically distributed bit error model for heavy-tailed wireless channels

The error patterns of a wireless channel can be represented by a binary sequence of ones (burst) and zeros (run), which is referred to as a trace. Recent surveys have shown that the run length distribution of a wireless channel is an intrinsically heavy-tailed distribution. Analytical models to characterize such features have to deal with the trade-off between complexity and accuracy. In this paper, we use an independent but not identically distributed (inid) stochastic process to characterize such channel behavior and show how to parameterize the inid bit error model on the basis of a trace. The proposed model has merely two parameters both having intuitive meanings and can be easily figured out from a trace. Compared with chaotic maps, the inid bit error model is simple for practical use but can still be deprived from heavy-tailed distribution in theory. Simulation results demonstrate that the inid model can match the trace, but with fewer parameters. We then propose an improvement on the inid model to capture the ‘bursty’ nature of channel errors, described by burst length distribution. Our theoretical analysis is supported by an experimental evaluation.

A Max-Plus Algebra Approach for Network-on-Chip End-to-End Delay Estimation

End-to-end delay is an important metric in Network-on-Chip (NoC) performance evaluation. Two kinds of approaches often utilized for evaluating the end-to-end delay of NoC are discrete-event simulation and theoretical analysis. The former one is widely used due to its high accuracy, but its extremely slow while performing large-scale NoC design space exploration. The later one is more efficient in fast performance evaluation. In this paper, we propose a max-plus algebra based NoC delay estimation approach, which can be used as an effective NoC design tool to estimate the end-to-end packet/flit delay. The proposal has no assumptions on the NoC topology, traffic pattern and hardware implementation methodologies, which makes it very attractive for fast performance evaluation. Experimental results show the fitness of our approach.

A Novel FEM Method of Modeling and Visualization

Ultrasonic transducer, as a measurement technique, gains more and more attention in Non-Destructive Testing and Evaluation (NDT&E) and imaging applications. It is important to know the propagation behaviors of ultrasonic waves in both of fluids and solids. Finite element method (FEM) has been widely used to solve partial differential equations (PDE) in wave propagation. In this paper, COMSOL is adopted due to its benefits in coupling of multiphysics modules and the simplicity in postprocessing. The properties of transient wave propagation in different kinds of media, such as piezoelectric solids, nonpiezoelectric solids and fluids, are modeled and simulated. The visualized wave modes confirmed the efficiency and simplicity of this approach.

An active buffer sizing algorithm for power-efficient NoC

In network-on-chips (NoCs), how to reduce the power consumption of router buffers has been a major concern. In this paper, we propose a methodology to minimize the power consumption of routers with meeting all the deadlines of traffic flows. First, we present a network calculus-based method to analyze the worst-case delay of each flow in NoC. By using the method, an active buffer sizing algorithm is proposed. The algorithm can find the optimal active size of each buffer, by iteratively reducing the size of active buffer units and checking if the deadlines are still met. Finally, the experimental results show that our method can save at most 20% of the total power consumption for NoC.

Newton's method based array subscripts dependence test framework

Auto-parallelization compilization is an essential way to obtain high efficient parallel code for High Performance Computers (HPCs) and Chip Multi-Processors (CMPs). For the parallelizing compilers, a fundamental step is array dependence analysis used for identifying the parallelizable code. Whereas, the existing dependence analysis approaches are only capable of recognizing few types of dependences, e.g. linear array subscript expressions or nonlinear monotonic subscript expressions, single or coupled subscripts, etc. The widely existing pseudo-dependence will prevent further optimization. In order to eliminate the pseudo-dependence as much as possible, many test algorithms should be integrated into compilers, which makes the compilers complex and redundant. In this paper, we propose a Newtons method based array subscript dependence test framework, and demonstrate our method by an practical example. Compared with the existing approaches, our framework supports both single and coupled subscripts, and has few constraints on the expressions of subscripts.

A novel network architecture for data center

To meet the requirements for a scalable, agile and efficient data center, we present DNet, a dual-network structure composed of a primary network and a secondary network. DNet is based on layer 2 fabric, which is considered more agile than layer 3 fabric in data center design. We compress ARP request and move it from the primary network to a secondary one, and we propose a DNet source routing protocol (DSR) for the primary network. We evaluate that, with these characteristics, DNet is enabled to scale to support huge data centers with up to 131K hosts. Besides, DSR simplifies switch design, and decreases the cost and delay.

Wireless Interconnects Enabled On-chip Multicast Communication

The ability of multicasting is necessary and useful for Chip Multiprocessors (CMPs) to benefit and implement cache coherence protocols, parallel algorithms, etc. Whereas the design and implementation of high-efficient multicasting in traditional wired Network-on-Chip (NoC) is an arduous task. With the aid of wireless interconnects, not only the bandwidth and latency of NoC can be improved dramatically, but also the inherent broadcast properties of wireless signals can be adopted for multicasting. In this paper, we propose a mesh-like multicast enhancing mechanism based on wireless interconnects. Equipped with 9 wireless transceivers in a traditional 9x9 mesh NoC, this approach realizes a high efficiency, low latency group interconnection. Simulation results show the promising performance boosting of the wireless interconnection.