Junhui Wang

Designing Voltage-Frequency Island Aware Power-Efficient NoC through Slack Optimization

In network-on-chips (NoCs), power consumption has become the main design constraint. In this paper, we propose a power-efficient network calculus-based (PNC) method to minimize the power consumption of NoC. Based on the slack that a packet can be further delayed in the network without violating its deadline, Our PNC method uses power-gating technique to reduce the active buffer size and uses voltage-frequency scaling technique to reduce the voltage-frequency of each voltage-frequency island. With less active buffer units and lower voltage- frequency, the power consumption of NoC is reduced. Experimental results show that our PNC method can save at most 50% of the total power consumption.

Analysis of worst-case backlog bounds for Networks-on-Chip

Abstract In networks-on-chips (NoCs), analyzing the worst-case backlog bounds of routers is very important to identify network congestions and improve network performance. In this paper, we propose a method called DiGB (DIrected-contention-Graph-based Backlog bound derivation) to analyze worst-case backlog bounds. For primitive scenarios, we propose analytical models for backlog bound derivation. For complex scenarios, we first construct a directed-contention-graph (DCG) to analyze the relationships among traffic flows. Then, we use the Breadth-First-Search strategy to traverse the DCG so that complex scenarios can be divided into primitive scenarios. Finally we compute the worst-case backlog bounds of each router. To illustrate this method, we present the derivation of closed-form formulas to compute the worst-case backlog bounds under all-to-one gather communication. The experimental results show that our method can achieve correct and tight worst-case backlog bounds.

An independent but not identically distributed bit error model for heavy-tailed wireless channels

The error patterns of a wireless channel can be represented by a binary sequence of ones (burst) and zeros (run), which is referred to as a trace. Recent surveys have shown that the run length distribution of a wireless channel is an intrinsically heavy-tailed distribution. Analytical models to characterize such features have to deal with the trade-off between complexity and accuracy. In this paper, we use an independent but not identically distributed (inid) stochastic process to characterize such channel behavior and show how to parameterize the inid bit error model on the basis of a trace. The proposed model has merely two parameters both having intuitive meanings and can be easily figured out from a trace. Compared with chaotic maps, the inid bit error model is simple for practical use but can still be deprived from heavy-tailed distribution in theory. Simulation results demonstrate that the inid model can match the trace, but with fewer parameters. We then propose an improvement on the inid model to capture the ‘bursty’ nature of channel errors, described by burst length distribution. Our theoretical analysis is supported by an experimental evaluation.

A Max-Plus Algebra Approach for Network-on-Chip End-to-End Delay Estimation

End-to-end delay is an important metric in Network-on-Chip (NoC) performance evaluation. Two kinds of approaches often utilized for evaluating the end-to-end delay of NoC are discrete-event simulation and theoretical analysis. The former one is widely used due to its high accuracy, but its extremely slow while performing large-scale NoC design space exploration. The later one is more efficient in fast performance evaluation. In this paper, we propose a max-plus algebra based NoC delay estimation approach, which can be used as an effective NoC design tool to estimate the end-to-end packet/flit delay. The proposal has no assumptions on the NoC topology, traffic pattern and hardware implementation methodologies, which makes it very attractive for fast performance evaluation. Experimental results show the fitness of our approach.

A Hybrid Hierarchical Software-Defined Photonic On-Chip Network

Photonic network and software-defined network are two promising technologies to improve the performance and scalability of on-chip network. However, both the technologies cannot address the problem alone. In this paper, we propose HaoDo, a hybrid hierarchical software-defined photonic On-Chip Network. The proposed architecture combines the advantages of photonic network and centralized control plane, and improve the scalability of whole network. The main contributions includes: we design HaoDo, a hybrid hierarchical control plane which can reduce the computational complexity growth of the SDN control plane and utilize the advantage of electronic short-distance communication and photonic long-distance communication, the hierarchical communication protocol is presented to guide the intr-/inter-area transmission. The discussions present the reason why the HaoDo network can achieve good performance and the possible design exploration for specific applications.

An active buffer sizing algorithm for power-efficient NoC

In network-on-chips (NoCs), how to reduce the power consumption of router buffers has been a major concern. In this paper, we propose a methodology to minimize the power consumption of routers with meeting all the deadlines of traffic flows. First, we present a network calculus-based method to analyze the worst-case delay of each flow in NoC. By using the method, an active buffer sizing algorithm is proposed. The algorithm can find the optimal active size of each buffer, by iteratively reducing the size of active buffer units and checking if the deadlines are still met. Finally, the experimental results show that our method can save at most 20% of the total power consumption for NoC.

A novel network architecture for data center

To meet the requirements for a scalable, agile and efficient data center, we present DNet, a dual-network structure composed of a primary network and a secondary network. DNet is based on layer 2 fabric, which is considered more agile than layer 3 fabric in data center design. We compress ARP request and move it from the primary network to a secondary one, and we propose a DNet source routing protocol (DSR) for the primary network. We evaluate that, with these characteristics, DNet is enabled to scale to support huge data centers with up to 131K hosts. Besides, DSR simplifies switch design, and decreases the cost and delay.

MIM: A new class of hybrid channel error model

Modeling and simulation on channel conditions play an important role in performance evaluation of wireless protocols. Two most widely used channel error model are independent model and Markov model. The former is simple and easy to implement, but cannot capture the bursty nature of channel errors. And we find that, when the bit error rate is relatively small, the existing Markov model cannot efficiently predict channel conditions. For these reasons, we propose MIM, a hybrid channel error model. MIM partitions the received binary indicator sequence into m blocks. And its assumed that the occurrence of bit errors within each block conforms to the two-state Markov model, while between blocks, block errors are independent and identically distributed (IID) as one fixed block error probability pb. We set up an office wireless environment and choose the optimal model parameters based on collected error trace. The analysis of model parameters shows that, our model well conforms to reality.

A Double-Links Scheme for DSDV in Mobile Ad Hoc Networks

To deal with invalid route reconstruction problems in Destination Sequenced Distance Vector (DSDV) routing protocol, a Double-Links scheme for DSDV, DLDSDV is proposed. The most distinguished characteristic of DLDSDV is that it needs not any new message exchange for invalid route reconstruction. However, it has to use more memory to store an extra routing table, the secondary routing table. When a node detects a link is broken, the node in DLDSDV employs the secondary routing table to find the neighbor quickly which has a valid route to the destination. We extend the path availability model for MANETs and derive an expression of path holding probability of DLDSDV. Simulation results show that DLDSDV improves the packet delivery ratio and has almost the same routing overhead and end-to-end delay as DSDV.

A hierarchical butterfly-based photonic Network-on-Chip

The demand of high-performance, scalable and energy-efficient on-chip interconnection network are growing in many-core processors. However, the limitations of the metallic interconnect make electronic Network-on-Chip inefficient. Photonic on-chip networks with advanced CMOS-compatible photonic devices, brings a bright future. In this paper, we present a hierarchical butterfly-based photonic Network-on-Chip, with hybrid router, its topology, and the communication protocol. The proposed network leverages the electronic and photonic technology to improve on-chip network performance. HBPNoC uses hierarchical architecture for packet switching in intra-cluster networks and circuit switching in the inter-cluster network. A butterfly-based structure, comprised of 2×2 photonic switching elements, is used for inter-cluster communication. The simulation results show that our proposed network has very good performance with low optical loss.