Barry W. Johnson

Capturing design rationale in concurrent engineering teams

It is argued that a hardware/software codesign methodology should support the following capabilities: integration of the hardware and software design processes; exploration of hardware/software tradeoffs and evaluation of hardware/software alternatives; and model continuity. A codesign methodology that supports many of these capabilities is outlined. The methodology is iterative in nature and serves to guide codesign exploration with the uninterpreted/interpreted modeling approach. It integrates performance (uninterpreted) models and functional (interpreted) models in a common simulation environment. >It is argued that a hardware/software codesign methodology should support the following capabilities: integration of the hardware and software design processes; exploration of hardware/software tradeoffs and evaluation of hardware/software alternatives; and model continuity. A codesign methodology that supports many of these capabilities is outlined. The methodology is iterative in nature and serves to guide codesign exploration with the uninterpreted/interpreted modeling approach. It integrates performance (uninterpreted) models and functional (interpreted) models in a common simulation environment.<<ETX>>

Object-oriented techniques in hardware design

We focus on using object-oriented techniques to improve the hardware design process. The advantages of these techniques for hardware design include: improved modifiability and maintainability of models; easy component instantiation with different parameters; quick composition of new components; the ability to identify and reuse common components; the ability to tailor general-purpose components to more specialized components; support of dynamic object creation and destruction; and the possibility of employing existing software synthesis and verification techniques. We illustrate the application of object-oriented techniques using a load-store, reduced instruction-set processor that contains a local memory. The instruction set consists of 22 instructions, which require one or two 16-bit words. Arithmetic is performed in twos complement. We use C++ to demonstrate the usefulness of object-oriented techniques, not to provide arguments for or against its use in hardware modeling and design.<<ETX>>

Reliability modeling of hardware/software systems

This paper uses a single model to analyze the effects of both hardware and software on system reliability. A unified model of hardware and software reliability is developed using Markov modeling. Then the effect of hardware and software failures is studied using the model. The model incorporates concepts from both hardware and software reliability modeling. Examples of both simplex (nonredundant) and redundant architectures are analyzed using the model. >

Fault-Tolerant Microprocessor-Based Systems

How do computers go wrong and what can we do about it? This tutorial outlines the causes of faults and the basic techniques for dealing with them.

Dependability metrics to assess safety-critical systems

Metrics are commonly used in engineering as measures of the performance of a system for a given attribute. For instance, in the assessment of fault tolerant systems, metrics such as the reliability, R(t) and the Mean Time To Failure (MTTF) are well-accepted as a means to quantify the fault tolerant attributes of a system with an associated failure rate, /spl lambda/. Unfortunately, there does not seem to be a consensus on comparable metrics to use in the assessment of safety-critical systems. The objective of this paper is to develop two metrics that can be used in the assessment of safety-critical systems, the steady-state safety, S/sub ss/, and the Mean Time To Unsafe Failure (MTTUF). S/sub ss/ represents the evaluation of the safety as a function of time, in the limiting case as time approaches infinity. The MTTUF represents the average or mean time that a system will operate safely before a failure that produces an unsafe system state. A 3-state Markov model is used to model a safety-critical system with the transition rates computed as a function of the system coverage C/sub sys/, and the hazard rate /spl lambda/(t). Also, /spl lambda/(t) is defined by the Weibull distribution, primarily because it allows one to easily represent the scenarios where the failure rate is increasing, decreasing, and constant. The results of the paper demonstrate that conservative estimates for lower bounds for both S/sub ss/ & the MTTUF result when C/sub sys/ is assumed to be a constant regardless of the behavior of /spl lambda/(t). The derived results are then used to evaluate three example systems.

Transient fault models and AVF estimation revisited

Transient faults (also known as soft-errors) resulting from high-energy particle strikes on silicon are typically modeled as single bit-flips in memory arrays. Most Architectural Vulnerability Factor (AVF) analyses assume this model. However, accelerated radiation tests on static random access memory (SRAM) arrays built using modern technologies show evidence of clustered upsets resulting from single particle strikes. In this paper, these observations are used to define a scalable fault model capable of representing fault multiplicities. Applying this model, a probabilistic framework for incorporating vulnerability of SRAM arrays to different fault multiplicities into AVF is proposed. An experimental fault injection setup using a detailed microarchitecture simulation running generic benchmarks was used to demonstrate vulnerability characterization in light of the new fault model. Further, rigorous fault injection is used to demonstrate that conventional methods of AVF estimation overestimate vulnerability up to 7× for some structures.

Behavioral fault modeling in a VHDL synthesis environment

This paper proposes new fault models for VHDL behavioral descriptions of combinational logic circuits. The models are developed via abstraction of industry standard single-stuck-line (SSL) faults into the behavioral domain. A functional analysis technique is used to evaluate the effects of SSL faults on gate level implementations. Generalized functional faults are then abstracted into the behavioral domain by examining their relationship with the higher level language construct. Test vectors derived from the new behavioral fault models are applied to synthesized gate level realizations of an example arithmetic logic unit. Resulting gate level fault coverage is determined and used as a measure of effectiveness for the new fault models. Because the behavioral faults are derived from a functional analysis of low level faults, they provide improved fault coverage over previous fault models.

Design, implementation, and testing of an adaptable optimal controller for an electric wheelchair

The authors present the design, implementation, and testing of an adaptable, optimal controller for the electric wheelchair. Optimal control theory and pattern recognition techniques are combined to design a variable-structure controller (VSC) using a modified proportional, integral, and derivative (PID) control method. The controller is adaptable in the sense that multiple sets of control coefficients are used, with each set being optimized for a specific range of wheelchair load parameters. The appropriate set of control coefficients can be automatically selected on the basis of load parameter estimates to provide a self-adaptive controller, or manually selected prior to installation to tailor the chair to a particular user. The manually adaptable controller is implemented in a microprocessor-based system, installed on an electric wheelchair, and its performance is experimentally verified.<<ETX>>

Dynamic Modeling of an Electric Wheelchair

The development of a dynamic model for the standard electric wheelchair is described. A computer simulation of the nonlinear differential equations of motion that resulted was developed. In order to verify the modeling process, an electric wheelchair was instrumented to record rear wheel velocities and caster orientations as a function of time. The simulation program has been used to study appropriate control algorithms to be implemented in a new digital controller design for the electric wheelchair.

System-level modeling in the ADEPT environment of a distributed computer system for real-time applications

The design of complex systems in safety-critical applications requires an integrated design and assessment environment. The paper presents the ADEPT environment for designing dependable systems from concept to implementation. An application of ADEPT to modeling a distributed computer system used in real-time embedded train control applications is described. Results from a performance analysis of the distributed computer system model are illustrated. Dependability results are also presented for a second example application.<<ETX>>