James H. Aylor

Body Area Sensor Networks: Challenges and Opportunities

Body area sensors can enable novel applications in and beyond healthcare, but research must address obstacles such as size, cost, compatibility, and perceived value before networks that use such sensors can become widespread.

Capturing design rationale in concurrent engineering teams

It is argued that a hardware/software codesign methodology should support the following capabilities: integration of the hardware and software design processes; exploration of hardware/software tradeoffs and evaluation of hardware/software alternatives; and model continuity. A codesign methodology that supports many of these capabilities is outlined. The methodology is iterative in nature and serves to guide codesign exploration with the uninterpreted/interpreted modeling approach. It integrates performance (uninterpreted) models and functional (interpreted) models in a common simulation environment. >It is argued that a hardware/software codesign methodology should support the following capabilities: integration of the hardware and software design processes; exploration of hardware/software tradeoffs and evaluation of hardware/software alternatives; and model continuity. A codesign methodology that supports many of these capabilities is outlined. The methodology is iterative in nature and serves to guide codesign exploration with the uninterpreted/interpreted modeling approach. It integrates performance (uninterpreted) models and functional (interpreted) models in a common simulation environment.<<ETX>>

A battery state-of-charge indicator for electric wheelchairs

Deep-discharge-type lead-acid batteries used in most electric wheelchairs require acurrate battery state-of-charge indication to prevent stranding and to provide economical operation of the wheelchair. A monitoring technique combining the open-circuit voltage and the coulometric measurements had been previously implemented on a microcomputer-based circuit. This adaptive monitoring technique enables the monitor to adjust to different battery sizes as well as the aging process. Several improvements are reported. A technique has been developed to enhance the acurracy and reduce the required rest period of the open-circuit voltage measurement. The open-circuit voltage recovery curve is approximated by two asymptotes on a semilog scale. The open-circuit voltage is then extrapolated from the slope of the first asymptote before it fully stabilizes. The accuracy of the monitor has been verified in field tests, and comparison with a commercial battery monitor shows it to be superior in several respects. >

System lifetime optimization for heterogeneous sensor networks with a hub-spoke technology

As a specific area of sensor networks, wireless in-home sensor networks differ from general sensor networks in that the network has nodes with heterogeneous resources and dissimilar mobility attributes. For example, sensor with different radio coverage, energy capacity, and processing capabilities are deployed, and some of the sensors are mobile and others are fixed in position. The architecture and routing protocol for this type of heterogeneous sensor networks must be based on the resources and characteristics of their member nodes. In addition, the sole stress on energy efficiency for performance measurement is not sufficient. System lifetime is more important in this case. We propose a hub-spoke network topology that is adaptively formed according to the resources of its members. A protocol named resource oriented protocol (ROP) was developed to build the network topology. This protocol principally divides the network operation into two phases. In the topology formation phase, nodes report their available resource characteristics, based on which network architecture is optimally built. We stress that due to the existence of nodes with limitless resources, a top-down appointment process can build the architecture with minimum resource consumption of ordinary nodes. In the topology update phase, mobile sensors and isolated sensors are accepted into the network with an optimal balance of resources. To avoid overhead of periodic route updates, we use a reactive strategy to maintain route cache. Simulation results show that the hub-spoke topology built by ROP can achieve much longer system lifetime.

Dynamic access ordering for streamed computations

Memory bandwidth is rapidly becoming the limiting performance factor for many applications, particularly for streaming computations such as scientific vector processing or multimedia (de)compression. Although these computations lack the temporal locality of reference that makes traditional caching schemes effective, they have predictable access patterns. Since most modern DRAM components support modes that make it possible to perform some access sequences faster than others, the predictability of the stream accesses makes it possible to reorder them to get better memory performance. We describe a Stream Memory Controller (SMC) system that combines compile-time detection of streams with execution-time selection of the access order and issue. The SMC effectively prefetches read-streams, buffers write-streams, and reorders the accesses to exploit the existing memory bandwidth as much as possible. Unlike most other hardware prefetching or stream buffer designs, this system does not increase bandwidth requirements. The SMC is practical to implement, using existing compiler technology and requiring only a modest amount of special purpose hardware. We present simulation results for fast-page mode and Rambus DRAM memory systems and we describe a prototype system with which we have observed performance improvements for inner loops by factors of 13 over traditional access methods.

Object-oriented techniques in hardware design

We focus on using object-oriented techniques to improve the hardware design process. The advantages of these techniques for hardware design include: improved modifiability and maintainability of models; easy component instantiation with different parameters; quick composition of new components; the ability to identify and reuse common components; the ability to tailor general-purpose components to more specialized components; support of dynamic object creation and destruction; and the possibility of employing existing software synthesis and verification techniques. We illustrate the application of object-oriented techniques using a load-store, reduced instruction-set processor that contains a local memory. The instruction set consists of 22 instructions, which require one or two 16-bit words. Arithmetic is performed in twos complement. We use C++ to demonstrate the usefulness of object-oriented techniques, not to provide arguments for or against its use in hardware modeling and design.<<ETX>>

Access order and effective bandwidth for streams on a Direct Rambus memory

Processor speeds are increasing rapidly and memory speeds are not keeping up. Streaming computations (such as multimedia or scientific applications) are among those whose performance is most limited by the memory bottleneck. Rambus hopes to bridge the processor/memory performance gap with a recently introduced DRAM that can deliver up to 1.6 Gbytes/sec. We analyze the performance of these interesting new memory devices on the inner loops of streaming computations, both for traditional memory controllers that treat all DRAM transactions as random cacheline accesses, and for controllers augmented with streaming hardware. For our benchmarks, we find that accessing unit-stride streams in cacheline bursts in the natural order of the computation exploits from 44-76% of the peak bandwidth of a memory system composed of a single Direct RDRAM device, and that accessing streams via a streaming mechanism with a simple access ordering scheme can improve performance by factors of 1.18 to 2.25.

Reliability modeling of hardware/software systems

This paper uses a single model to analyze the effects of both hardware and software on system reliability. A unified model of hardware and software reliability is developed using Markov modeling. Then the effect of hardware and software failures is studied using the model. The model incorporates concepts from both hardware and software reliability modeling. Examples of both simplex (nonredundant) and redundant architectures are analyzed using the model. >

Smarter memory: improving bandwidth for streamed references

Processor speeds are increasing so much faster than memory speeds that within a decade processors may spend most of their time waiting for data. Most modern DRAM components support modes that make it possible to perform some access sequences more quickly than others. The authors describe how reordering streams can result in better memory performance.

Parallel-processing techniques for automatic test pattern generation

Some of the more widely used serial automatic test pattern generation (ATPG) algorithms and their stability for implementation on a parallel machine are discussed. The basic classes of parallel machines are examined to determine what characteristics they require of an algorithm if they are to implement it efficiently. Several techniques that have been used to parallelize ATPG are presented. They fall into five major categories: fault partitioning, heuristic parallelization, search-space partitioning, functional (algorithmic) partitioning, and topological partitioning. In each category, an overview is given of the technique, its advantages and disadvantages, the type of parallel machine it has been implemented on, and the results.<<ETX>>