Bart Vermeulen

Design for debug: catching design errors in digital chips

For large, complex ICs, engineers need efficient techniques for debugging first silicon. The system presented here consists of an on-chip debug infrastructure and supporting debugger software,which interacts with the infrastructure to make the chips features accessible through a serial interface.

Core-based scan architecture for silicon debug

In this paper, we present a core-based scan architecture for silicon debug, which is currently being standardized within Philips. The reasons behind the core-based debug architecture, together with implementation details, are described. The choices that were made during its development are explained using the experiences gained from two large Philips system chips that each utilize core-based design and test, and scan-based silicon debug. The results of an area-cost evaluation of the presented architecture for these two large system chips are also presented.

Silicon debug: scan chains alone are not enough

For todays multi-million transistor designs, existing design verification techniques cannot guarantee that first silicon is designed error free. Therefore, techniques are necessary to efficiently debug first-silicon. In this article, we present a methodology for debugging multiple clock domain systems-on-a-chip. In addition to scan chains, a set of design-for-debug modules is designed into an IC to make it debuggable. Debugger tool software interacts with the on-chip DfD to make the debug features available from a workstation.

Functional Debug Techniques for Embedded Systems

Some problems in a new chip design or its embedded software show up only when a silicon prototype of the chip is placed in its intended target environment and the embedded software is executed. Traditionally, embedded-system debug is very difficult and time-consuming because of the intrinsic lack of internal system observability in the target environment. Design for debug (DFD) is the act of adding debug support to a chips design in the realization that not every silicon chip or embedded-software application is right the first time. In the past few years, functional debug has made significant progress. This article describes the most common structured approaches available for silicon debug of embedded systems.

Automatic generation of breakpoint hardware for silicon debug

Scan-based silicon debug is a technique that can be used to help find design errors in prototype silicon more quickly. One part of this technique involves the inclusion of breakpoint modules during the design stage of the chip. This paper focuses on an innovative approach to automatically generate breakpoint modules by means of a breakpoint description language. This language is illustrated using an example, and experimental results are presented that show the efficiency and effectiveness of this new method for generating breakpoint hardware.

Transaction-Based Communication-Centric Debug

The behaviour of systems on chip (SOC) is complex because they contain multiple processors that interact through concurrent interconnects, such as networks on chip (NOC). Debugging such SOCs is hard. Based on a classification of debug scope and granularity, we propose that debugging should be communication-centric and based on transactions. Communication-centric debug focuses on the communication and the synchronisation between the IP blocks, which are implemented by the interconnect using transactions. We define and implement a modular debug architecture, based on NOC, monitors, and a dedicated high-speed event-distribution broadcast interconnect. The manufacturing-test scan chains and IEEE1149.1 test access ports (TAP) are re-used for configuration and debug data read-out. Our debug architecture requires only small changes to the functional architecture. The additional area cost is limited to the monitors and the event distribution interconnect, which are 4.5% of the NOC area, or less than 0.2% of the SOC area. The debug architecture runs at NOC functional speed and reacts very quickly to debug events to stop the SOC close in time to the condition that raised the event. The speed at which data is retrieved from the SOC after stopping using the TAP is 10 MHz. We prove our concepts and architecture with a gate-level implementation that includes the NOC, event distribution interconnect, and clock, reset, and TAP controllers. We include gate-level signal traces illustrating debug at message and transaction levels

Test and debug strategy of the PNX8525 Nexperia/sup TM/ digital video platform system chip

Decreasing feature sizes and increasing customer demand for more functionality have forced design teams to re-use design blocks and application platforms. As a result, re-use of test, design-for-test and design-for-debug for large system chips is becoming increasingly important and increasingly necessary.. In this paper, the test and debug features of the Nexperia/sup TM/ PNX8525 chip are presented. The PNX8525 chip is a large system chip for the consumer electronics market. The impact of core-based testing is discussed, at both the core-level and the top-level, together with the design-for-debug implementation on this multiple clock domain chip.

IEEE 1149.1-compliant access architecture for multiple core debug on digital system chips

To enable the efficient use of debug functionality on a core-based system chip, existing core-level debug interfaces need to be re-used in one, well-defined debug architectures at chip-level. This paper describes a chip-level architecture for controlling multiple IEEE 1149.1 compliant debug interfaces on a single system chip. The presented architecture is not only fully compliant with IEEE 1149.1 with regard to the chip-level debug and boundary scan hardware, but also as to whether or not the bypass multiplexer is activated. Chip-level TAP support is also presented to allow multiple debugger tools to control debug operations in multiple heterogeneous cores via this architecture. As an experiment, the proposed architecture is mapped on an FPGA to verify concurrent debug of multiple cores.

Silicon debug of a co-processor array for video applications

For todays multi-million transistor ICs, existing design verification techniques cannot guarantee that first silicon is designed error free. Because of this reality, there is a need for a good debug methodology. This paper describes the application of a generic silicon debug methodology to a modular video-processing chip called co-processor array (CPA). The debug hardware, which was added to the design, and the supporting debugger software are described. The application of the added debug functionality and its effectiveness during first silicon bring-up are also presented.

A Network-on-Chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs

Problems in a new System on Chip (SOC) consisting of hardware and embedded software often only show up when a silicon prototype of the chip is placed in its intended target environment and the application is executed. Traditionally, the debugging of embedded systems is difficult and time consuming because of the intrinsic lack of internal system observability and controlability in the target environment. Design for Debug (DfD) is the act of adding debug support to the design of a chip, in the realization that not every SOC is correct first time. DfD provides debug engineers with increased observability and controlability of the internal operation of an embedded system. In this paper, we present a monitoring infrastructure for multi-processor SOCs with a Network on Chip (NOC), and explain its application to performance analysis and debug. We describe how our monitors aid in the performance analysis and debug of the interactions of the embedded processors. We present a generic template for bus and router monitors, and show how they are instantiated at design time in our NOC design flow. We conclude this paper with details of their hardware cost.