Hans G. Kerkhoff

Testing Microelectronic Biofluidic Systems

Biochips can fail because of a wide variety of reasons, ranging from electrical defects (shorts, opens, and so on) to material properties, unexpected fluidic flow patterns, and chemical or biological contamination. This article describes the way to detect and locate various types of faults in biochips. This article describes analog and digital microelectronic fluidic (MEF) arrays design and testing methods.

Testable design and testing of micro-electro-fluidic arrays

The testable design and testing of a fully software-controllable lab-on-a-chip, including a fluidic array of FlowFETs, control and interface electronics is presented. Test hardware is included for detecting faults in the DMOS electro-fluidic interface and the digital parts. Multidomain fault modeling and simulation shows the effects of faults in the (combined) fluidic and electrical parts. The fault simulations also reveal important parameters of multi-domain test-stimuli, e.g. fluid velocity, for detecting both electrical and fluidic defects.

Testability analysis of analog systems

A method is presented to analyze the testability of both linear and nonlinear analog systems. It combines a rank-test algorithm with statistical methods. The algorithm will find sets of dependent parameters and determine whether it is possible to calculate a certain parameter with sufficient accuracy. it also determines a subset of appropriate measurements if redundant measurements are present. >

Fault Modeling and Fault Simulation in Mixed Micro-Fluidic Microelectronic Systems

Developments in electronic/fluidic microsystems are progressing rapidly. The ultimate goal is to deliver products in the 10,000 fluidic reaction-wells range. Exciting applications include massive parallel DNA analysis and automatic drug synthesis. Until now, only functional testing has been used to “guarantee” the quality of micro-fluidic systems after manufacturing.In this paper, defect-oriented test approaches developed in analogue fault modeling and simulation have been used to predict for the first time the faulty behavior of micro-electronic fluidic microsystems. The modeling is targeted for use in complex electronic/fluidic microsystems employing commercial microsystem CAD tools. It enables a measure for the quality of these systems based on the performed (functional) tests and can be a guide for future test-stimuli generation and yield prediction.

Structural computer-aided design of current-mode CMOS logic circuits

A set of CAD (computer-aided design) tools for the synthesis and layout generation of multiple-valued current-mode CMOS logic (CMCL) circuits is described. The synthesis method is based on the cost-table method. The general circuit structure, the cost-table functions, and the decomposition procedure used in the synthesis program are explained. The program is based on a logically complete set of basic elements for CMCL circuits. After circuit synthesis, the actual layout is generated using standard-cell IC design tools.<<ETX>>

Designing and implementing an architecture with boundary scan

A description is given of a standardized structured test methodology based on the boundary-scan proposal from the Joint Test Action Group (JTAG), which is now IEEE proposed standard P1149.1. Boundary scan does not address testability at the IC level, primarily because there is no standard for designing built-in self-testing (BIST) circuits. An architecture called the hierarchical testable, or H-testable, architecture that is compatible with the JTAG boundary-scan standard for PCB testing and provides BIST at the IC level is presented. The two have been merged, ensuring testability of the hardware from the printed-circuit-board level down to integrated-circuit level. In addition, the architecture has built-in self-test at the IC level. The authors have implemented this design using a self-test compiler.<<ETX>>

CRISP: Cutting Edge Reconfigurable ICs for Stream Processing

The Cutting edge Reconfigurable ICs for Stream Processing (CRISP) project aims to create a highly scalable and dependable reconfigurable system concept for a wide range of tomorrow’s streaming DSP applications. Within CRISP, a network-on-chip based many-core stream processor with dependability infrastructure and run-time resource management is devised, implemented, and manufactured to demonstrate a coarse-grained core-level reconfigurable system with scalable computing power, flexibility, and dependability. This chapter introduces CRISP, presents the concepts, and outlines the preliminary results of a running project.

Design of an Infrastructural IP Dependability Manager for a Dependable Reconfigurable Many-Core Processor

Reconfigurable many-core processors have many advantages over conventionally designed devices, such as low power consumption and very high flexibility. For an increasing number of safety-critical applications, these processors must have an ultra high dependability. This paper discusses the design and verification of an infrastructural IP, the Dependability Manager, which takes care of most essential dependability issues. Several additional innovative approaches with regard to dependability have been incorporated, like the NoC, wrapper and Network Interface design. The Dependability Manager design has been verified on an FPGA and is being processed in UMC CMOS technology as part of a many-core processor.

Automatic scan insertion and test generation for asynchronous circuits

A test method for asynchronous handshake circuits is presented that is based on synchronous full-scan techniques. The method adds a synchronous test mode to the circuit, in which the entire circuit is controlled by external clocks. This enables the use of conventional test generation tools. The method resulted in an operational flow, capable of automatically testing any handshake circuit with test-quality equal to synchronous circuits. Several circuits have been evaluated, demonstrating over 99% stuck-at fault coverage.

Tackling test trade-offs from design, manufacturing to market using economic modeling

This paper presents a general economic modeling methodology for digital semiconductor production test approaches. The methodology can be used to quantify trade-offs and evaluate test approaches, including distributed test across test insertions, multi-site test, on-chip/off-chip test trade-offs and ATE architectural tradeoffs, with modeled cost contributions that include test time, die area, yield, time-to-market, and engineering effort. It allows one to forecast how those test approaches scale with technology progress. The economic models are modular and expandable. The modeling methodology will be illustrated on various test approaches.