Bassem Mouawad

Direct Copper Bonding for Power Interconnects: Design, Manufacturing, and Test

3-D power module structures allow for better cooling and lower parasitic inductances compared with the classical planar technology. In this paper, we present a 3-D technology that uses an innovative assembly method (direct copper-to-copper bonding). The concept and manufacturing process of this technology is described in detail. An accurate electrical characterization is then performed to compare its performance with that of the classical planar structures.

Application of the Spark Plasma Sintering Technique to Low-Temperature Copper Bonding

Planar structures, in which a power die is soldered on a substrate and wirebonds are used to connect the top of the die with the substrate, are limited in terms of thermal management and power density. 3-D packaging techniques have been proposed to overcome these limits. Here, an innovative copper-to-copper bonding solution is presented, that can be used for 3-D packaging. The bonding process is described and the effect of the bonding parameters is investigated. It is found that this technique is compatible with the requirements of power electronic packaging. A test assembly including a silicon power die and ceramic substrates is presented.

Elaboration of Architectured Materials by Spark Plasma Sintering

Spark plasma sintering has been used for decades in order to consolidate a wide variety of materials and permitting to obtain fully dense specimens. This technique has been mainly applied to ceramics. This paper concentrates on an unusual use of spark plasma sintering system: obtaining innovative materials especially architectured ones. Different applications are presented. Firstly, the SPS technique has been used to elaborate nanometers grain size materials or containing nanoscale microstructure. This is possible since the sintering temperature and the holding time are far lower in the SPS compared to other techniques. Then SPS has been used to realize diffusion bonding. In that case again, bonding can be realized at low temperature and for short time. It permits for example to realize bonding between two copper layers which is of a great importance for microelectronic applications. It is worth noting that this bonding can have the same mechanical strength as pure copper even for diffusion time of a few minutes. Secondly, bonding has been also carried out between a metallic layer and a ceramic one. This could lead to design of new layered materials combining interesting properties in terms of mechanical strength but also in terms of electrical resistance. The SPS machine has also been used to obtain porous materials (cobalt alloys or copper) with an adapted microstructure (porosity, tortuosity,). These structures could open new perspectives for biomedical or for microelectronic applications. All these examples lead to a better understanding of the physical processes which happen during spark plasma sintering.

Hybrid half-bridge package for high voltage application

3D power module structures allow for better cooling and lower parasitic inductances compared with the classical planar technology. In this paper, we present a hybrid half-bridge in a 3D packaging configuration, dedicated for high voltage application. A dynamic electrical test of the package is presented.

Low parasitic inductance multi-chip SiC devices packaging technology

This paper presents a novel packaging structure which employs stacked substrate and flexible printed circuit board (PCB) to obtain very low parasitic inductance and hence feature high switching speed SiC power devices. A half-bridge module aimed at blocking voltage up to 2.5kV has been designed to accommodate 8 SiC JFETs and 4 SiC diodes. Electromagnetic simulation results reveal extremely low inductance values of the major loops. Then the prototyping of the designed package including the assembly process, all the electrical test to evaluate the electrical performance are presented.

Mechanical Study of Copper Bonded at Low Temperature Using Spark Plasma Sintering Process

Bonding of high purity polished copper was investigated using the Spark Plasma Sintering technique (SPS) showing the effect of SPS parameters (surface roughness, time, temperature and pressure) on the bonding strength behaviour. Mechanical characterization of the bonded samples was performed at room temperature using tensile test. Two surfaces roughnesses were studied (un-polished and polished samples). It was found that the bonding strength varied from 50 MPa to 233 MPa for un-polished and polished surfaces respectively The tensile strength of the used bulk copper-rod was found to be 365 MPa, while most results are over 122 MPa (a third of the bulk value).

A thermal cycling reliability study of ultrasonically bonded copper wires

In this work we report on a reliability investigation regarding heavy copper wires ultrasonically bonded onto active braze copper substrates. The results obtained from both a non-destructive approach using 3D X-ray tomography and shear tests showed no discernible degradation or wear out from initial conditions to 2900 passive thermal cycles from − 55 to 125 °C. Instead, an apparent increase in shear strength is observed as the number of thermal cycles increases. Nanoindentation hardness investigations suggest the occurrence of cyclic hardening. Microstructural investigations of the interfacial morphologies before and after cycling and after shear testing are also presented and discussed.

Chip-on-board assembly of 800V Si L-IGBTs for high performance ultra-compact LED drivers

This paper presents a novel chip on board assembly design for an integrated power switch, based on high power density 800V silicon lateral insulated gate bipolar transistor (Si LIGBT) technology. LIGBTs offer much higher current densities (5-lOX), significantly lower leakage currents, lower parasitic device capacitances and gate charge compared to conventional vertical MOSFETs commonly used in LED drivers. The higher voltage ratings offered (up to 1kV), the development of high voltage interconnection between parallel IGBTs, self-isolated nature and absence of termination region unlike in a vertical MOSFET makes these devices ideal for ultra-compact, low bill of materials (BOM) count LED drives. Chip on-board LIGBTs also offer significant advantages over MOSFETs due to high temperatures seen on most of the LED lamp enclosures as the LIGBTs on-state losses increase only marginally with temperature. The design is based on a built-in reliability approach which focuses on a compact LED driver as a case-study of a cost-sensitive large volume production item.

Design of a novel, high-density, high-speed 10 kV SiC MOSFET module

High-density packaging of fast-switching power semiconductors typically requires low thermal resistance and parasitic inductance. High-density packaging of high-voltage semiconductors, such as 10 kV SiC MOSFETs, has the added challenge of maintaining low electric field concentration in order to prevent premature dielectric breakdown. This work proposes a wire-bond-less, sandwich structure with embedded decoupling capacitors and stacked ceramic substrates in order to realize a high-density module capable of high-speed switching with low electric field concentration and EMI. This is the first time that these advanced packaging techniques have been applied to a 10 kV SiC MOSFET module.

Reliable Integration of a high performance multi-chip half-bridge SiC power module

Silicon carbide (SiC) devices have been adopted to push the boundaries further in terms of power density, conversion efficiency, switching speed or thermal capability. To have the benefit of such semiconductors, new packaging should be developed to meet all the advantages. In this paper, we present a reliable integrated concept of a new packaging solution for multi-chip SiC devices aiming to have a very low parasitic inductance in order to have high switching frequencies and ensure a good reliability for long-term operation.