Beatriz Blanco-Filgueira

A Verilog-AMS photodiode model including lateral effects

The market of CMOS image sensors is rapidly gaining an importance since optoelectronic devices are present in an increasing number of electronic systems. Therefore, accurate scalable optoelectronic models for photodetectors are necessary to predict their behaviour by circuit simulation. Hardware description languages (HDLs) offer an effective and efficient way to describe these systems. In this work, a Verilog-AMS model for the photoresponse of a CMOS photodiode including lateral effects is presented and a simplified equivalent electrical circuit of the photodiode is used to simulate two different pixel cells in Cadence framework.

Experimental characterization of peripheral photocurrent in CMOS photodiodes down to 65?nm technology

In this work, an in-depth experimental characterization of submicron CMOS p–n+ junction photodiodes operating under uniform illumination in the visible range is performed. The experimental measurements are used to validate a previous two-dimensional analytical model for the photoresponse estimation of these structures, which pays special attention to the lateral collection and was verified by means of device simulations. To do so, square p–n+ junction photodiodes with different sizes down to an active area of 0.56 μm wide have been fabricated in 180 and 65 nm technological nodes and characterized under blue, green and red light sources. As a result, the importance of the lateral collection in the overall response for small photodiodes that was previously theoretically reported is confirmed. The experimentally validated two-dimensional analytical model is a powerful tool that can be employed for the design of CMOS imagers and related electronics circuits.

A Review of CMOS Photodiode Modeling and the Role of the Lateral Photoresponse

The CMOS photodiode is the primary photosensing device used in solid-state image sensors. A review of significant CMOS photodiode models that can be found in the literature in recent years is presented here. We have focused on photocurrent models in one, two, and three dimensions, paying special attention to lateral current components. Lateral collection, particularly for small devices fabricated in deep submicrometer technologies, has been shown to be of utmost importance. Finally, several models to account for crosstalk effects are also described.

Bottom collection of photodiode-based CMOS APS

The market for solid-state image sensors has been experiencing an explosive growth in recent years resulting in CMOS sensors rapidly becoming one of the emerging sectors with more projection potential in the semiconductors industry. A CMOS active pixel sensor (APS) with a reverse biased p-n junction photodiode constitutes the structure of more widespread use, and it has been made a viable alternative to CCDs with the advent of deep submicron CMOS technologies and microlenses. Peripheral area of the junction depletion region plays an important role on collecting photocarriers in the vicinity of photodiode limits. In this paper, the peripheral photoresponse of CMOS APS of different dimensions in a deep submicron 0.18iquestm process is studied, paying special attention to the bottom collection.

Modeling and simulation of CMOS APS

This work studies the importance of the peripheral collection in the overall photoresponse in deep sub-micron CMOS 3T Active Pixel Sensors (APS), focusing on the contribution of the bottom surface of the depletion region. We analyze a semi-analytical expression, inspired by previous works, that models the photoresponse of a set of fabricated pixels with octagonal photodiodes that could be easily extended to different geometries. Device simulation results are used to study the behaviour of these structures with the purpose of using Computer Aided Design (CAD) tools for the next technological nodes researchs.

Dark current in standard CMOS pinned photodiodes for Time-of-Flight sensors

This paper deals with the optimal design of pinned photodiodes on standard CMOS technologies for Time-of-Flight sensors with the twofold objective of minimizing the dark current while ensuring an optimal charge transfer. The results are verified through CAD simulations with realistic doping profiles for a standard 0.18 μm CMOS technology. To the best of our knowledge, no similar analysis have been previously reported in the literature.

Closed-Form and Explicit Analytical Model for Crosstalk in CMOS Photodiodes

A closed-form and explicit 2-D analytical model for crosstalk(CTK) effects in p-n+ CMOS photodiodes for pixel design optimization has been developed in this paper. This model complements and extends a previous development describing the photocurrent because of the active area illumination along with the lateral depletion region and lateral components owing to the diffused photocarriers from the surroundings of the junction. The model has very few fitting parameters because it is physically based. Similarly, it can be of great use for CMOS image sensors designers, especially to fulfill high resolution and small area requirements by pixel size reduction. The model was validated extensively through device simulations with ATLAS and experimental data, and describes the CTK dependencies on light conditions and physical, geometrical, and process parameters.

Evidence of the lateral collection significance in small CMOS photodiodes

The lateral collection capacity of small CMOS photodiodes, scanned with a point source illumination, is studied. The mathematical solution of the physical equations is compared to experimental measurements in a standard UMC 90nm technology. They show close agreement and reveal that the lateral collection through the sidewalls of the depletion region becomes a significant component of the overall photocurrent. The same conclusion is achieved through device simulations under uniform illumination using ATLAS.

Analytical model for p-n junctions under point source illumination

An analyticalmodel of the photoresponse of p-n junctions under a point source illumination is presented. The model measures the response of different regions of the pixel in terms of current. Both p-n+ and p-Nwell junction photodiodes were fabricated in a standard UMC 90nm technology and tested. Model and experimental data reveal a similar behaviour.

A 2D model for radiation-hard CMOS annular transistors

Scaling benefits of CMOS processes include the reduction of the oxide thickness, which in turn favors the reduction of threshold voltage shifts due to radiation-induced gate oxide trapped charge. Moreover, experimental results have shown that this inherent radiation hardness of deep submicron processes can be further exploited using gate-enclosed layout transistors with an annular design. For an in-depth analysis of such structures, we present in this paper a 2D analytical I–V model for short-channel annular devices based on the direct solution of the Poisson equation in cylindrical coordinates. The theoretical approach is confirmed with experimental data in a standard CMOS 0.18 µm process.