Victor M. Brea

Cellular neural networks and active contours: a tool for image segmentation

Abstract In this paper Cellular Neural Networks (CNN) are applied to image segmentation based on active contour techniques. The approach is based on deformable contours which evolve pixel by pixel from their initial shapes and locations until delimiting the objects of interest. The contour shift is guided by external information from the image under consideration which attracts them towards the target characteristics (intensity extremes, edges, etc.) and by internal forces which try to maintain the smoothness of the contour curve. This CNN-based proposal combines the characteristics from implicit and parametric models. As a consequence a high flexibility and control for the evolution dynamics of the snakes are provided, allowing the solution of complex tasks as is the case of the topologic transformations. In addition the proposal is suitable for its implementation as an integrated circuit allowing to take advantages of the massively parallel processing in CNN to reduce processing time.

Discrete-time CNN for image segmentation by active contours

In this work we present a new image segmentation strategy which operates by means of active contours implemented on a multilayer cellular neural network. The approach consists of an expanding and thinning process, guided by external information from a contour which evolves until it reaches the final desired position in the image processed.

CMOS-3D Smart Imager Architectures for Feature Detection

This paper reports a multi-layered smart image sensor architecture for feature extraction based on detection of interest points. The architecture is conceived for 3-D integrated circuit technologies consisting of two layers (tiers) plus memory. The top tier includes sensing and processing circuitry aimed to perform Gaussian filtering and generate Gaussian pyramids in fully concurrent way. The circuitry in this tier operates in mixed-signal domain. It embeds in-pixel correlated double sampling, a switched-capacitor network for Gaussian pyramid generation, analog memories and a comparator for in-pixel analog-to-digital conversion. This tier can be further split into two for improved resolution; one containing the sensors and another containing a capacitor per sensor plus the mixed-signal processing circuitry. Regarding the bottom tier, it embeds digital circuitry entitled for the calculation of Harris, Hessian, and difference-of-Gaussian detectors. The overall system can hence be configured by the user to detect interest points by using the algorithm out of these three better suited to practical applications. The paper describes the different kind of algorithms featured and the circuitry employed at top and bottom tiers. The Gaussian pyramid is implemented with a switched-capacitor network in less than 50 μs, outperforming more conventional solutions.

Design of the processing core of a mixed-signal CMOS DTCNN chip for pixel-level snakes

This paper introduces the processing core of a full-custom mixed-signal CMOS chip intended for an active-contour-based technique, the so-called pixel-level snakes (PLS). Among the different parameters to optimize on the top-down design flow our methodology is focused on area. This approach results in a single-instruction-multiple-data chip implemented by a discrete-time cellular neural network with a correspondence between pixel and processing element. This is the first prototype for PLS; an integrated circuit with a 9/spl times/9 resolution manufactured in a 0.25 -/spl mu/m CMOS STMicroelectronics technology process. Awaiting for experimental results, HSPICE simulations prove the validity of the approach introduced here.

Image segmentation based on active contours using discrete time cellular neural networks

We present a new proposal for image segmentation using deformable models, as an application of discrete-time cellular neural networks (DTCNN). This approach is based on active contours (also called snakes) which evolve until reaching a final desired location. The contours are guided by both external information from the image under consideration which attracts them towards salient characteristics of the scene, and internal energy from the contour image which tries to maintain the smoothness in the curve shape. The massively parallel processing in DTCNN and the use of local information permit a VLSI implementation, suitable for real time applications.

A binary‐based on‐chip CNN solution for pixel‐level snakes

This paper introduces a binary-based on-chip cellular neural network (CNN) solution for pixel-level snakes. Every cell in the array comprises circuitry for B/W and grey-scale processing. The B/W processing is performed with a positive range high-gain discrete-time (DT)CNN model with 1-bit of programmability. The grey-scale processing is executed on a dedicated sub-cell. The design efforts are mainly focused on area consumption and processing speed. The result is a chip with a resolution of 9 × 9 cells in a 0.18 µm CMOS technology process and a density of more than 700cells/mm2. Simulations at schematic level lead to a time of less than 100ns for every DTCNN step. The peak power dissipation is kept at a few watts in a hypothetical chip of 128 × 128 cells. Copyright

SIMD/MIMD Dynamically-Reconfigurable Architecture for High-Performance Embedded Vision Systems

Image and video processing algorithms are becoming more and more sophisticated. An efficient hardware architecture is a requirement in order to address effectively the increasing computational workload. In a context of high performance, low cost and rapid prototyping, a hybrid SIMD/MIMD architecture for image processing is proposed in this work. By reusing functional units and including a dynamically reconfigurable datapath, this architecture enables high performance devices for general image processing tasks with high application development productivity when using as part of a System-on-Chip. A 32-bit 128-unit coprocessor was prototyped on a Virtex-6 FPGA and results show a peak performance of 19.6 GOP/s.

Switched-capacitor networks for scale-space generation

In scale-space filtering signals are represented at several scales, each conveying different details of the original signal. Every new scale is the result of a smoothing operator on a former scale. In image processing, scale-space filtering is widely used in feature extractors as the Scale-Invariant Feature Transform (SIFT) algorithm. RC networks are posed as valid scale-space generators in focal-plane processing. Switched-capacitor networks are another alternative, as different topologies and switching rate offer a great flexibility. This work examines the parallel and the bilinear implementations as two different switched-capacitor network topologies for scale-space filtering. The paper assesses the validity of both topologies as scale-space generators in focal-plane processing through object detection with the SIFT algorithm.

On the emulation of large-neighborhood templates with binary CNN-based architectures

This paper addresses the extension of applications covered by binary CNN-based architectures. The work is focused on diffusion-like tasks on binary images, traditionally tackled by either large neighborhood or propagating templates on CNNUM architecture. The solution adopted here is to split large neighborhood into smaller templates (3/spl times/3) on a binary CNN-based architecture. Trade-offs and hardware issues arisen from such an approach, as well as examples of application, are discussed throughout the paper.

FPGA-accelerated retinal vessel-tree extraction

This work introduces an FPGA implementation for vesseltree extraction on retinal images. The retinal vessel-tree can be used in disease diagnoses, e.g. diabetes, or in person authentication. In such cases, a portable device with a high performance may be a need. The FPGA implementation discussed here, although application-oriented, features a fully programmable SIMD architecture, allowing for an efficient realization of low-level image processing algorithms. It is mapped onto a Spartan 3, amounting to 90 processing elements. The on-chip memory utilized was 1.4MB and stores 8 gray images of 144 × 160px. The working frequency is 53MHz, allowing for a 3 × 3 convolution in less than 110μs.