Belle W. Y. Wei

High-performance architectures for elementary function generation

High-speed elementary function generation is crucial to the performance of many DSP applications. This paper presents three new architectures for generating elementary functions with IEEE single precision using second-order interpolation. These designs have been developed through a combination of architectural innovations and algorithm developments. They represent a range of trade-off between the use of memory modules and computational circuits. Our most memory intensive architecture uses one third less memory than alternative schemes while incurring no time penalty and minimal additional circuitry.

A parallel decoder of programmable Huffman codes

Huffman coding, a variable-length entropy coding scheme, is an integral component of international standards on image and video compression including high-definition television (HDTV). The high-bandwidth HDTV systems of data rate in excess of 100 Mpixels/s presents a challenge for designing a fast and economic circuit for intrinsically sequential Huffman decoding operations. This paper presents an algorithm and a circuit implementation for parallel decoding of programmable Huffman codes by using the numerical properties of Huffman codes. The 1.2 /spl mu/m CMOS implementation for a single JPEG AC table of 256 codewords of up to 16-b codeword lengths is estimated to run at 10 MHz with a chip area of 11 mm/sup 2/, decoding one codeword per cycle. The design can be pipelined to deliver a throughput of 80 MHz for decoding input streams of consecutive Huffman codes. Furthermore, our programmable scheme can be easily integrated into data paths of video processors to support different Huffman tables used in image/video applications. >

A VLSI architecture for a real-time code book generator and encoder of a vector quantizer

Image compression applications use vector quantization (VQ) for its high compression ratio and image quality. The current VQ hardware employs static instead of dynamic code book generation as the latter demands intensive computation and corresponding expensive hardware even though it offers better image quality. This paper describes a VLSI architecture for a real-time dynamic code book generator and encoder of 512/spl times/512 images at 30 frames/s. The four-chip 0.8 /spl mu/m CMOS design implements a tree of Kohonen self-organizing maps, and consists of two VQ processors and two image buffer memory chips. The pipelined VQ processor contains a computational core for both code book generation and encoding, and is scalable to processing larger frames. >

A complex-number multiplier using radix-4 digits

This paper describes the design of a 16/spl times/16 complex-number multiplier developed as part of the arithmetic datapath of a complex-number digital signal processor. The complex-number multiplier internally uses binary signed digits for fast multiplication and compact layout. It employs the traditional three-multiplication scheme while minimizing the logic and delay associated with the three extra pre-multiplication binary additions which that scheme requires. The minimization comes from producing the redundant binary sum for each of the pre-multiplication binary additions with minimal hardware, and then recoding the redundant sums as radix-4 multiplier operands. The radix-4 operands halve the number of summands to be added in each of the three real multiplier units. Furthermore, an additional factor of two reduction in the number of summands is effectuated by our coding scheme for representing binary signed digits. The result is a fast and compact complex-number multiplier.<<ETX>>

A single chip Lempel-Ziv data compressor

A single-chip implementation of the Lempel-Ziv adaptive data compression algorithm in 1.2-/spl mu/m CMOS technology is described. The chip uses 2K-byte on-chip content addressable memory (CAM)/SRAM for storing the most recent input characters to which the incoming string is compared against and referenced. It performs compression or decompression on byte-oriented input data at a data rate of one byte per clock cycle, except when one out of every 33 cycles is used to update the string dictionary.<<ETX>>

High-performance VLSI multiplier with a new redundant binary coding

This paper describes the design of a 16×16 redundant binary multiplier for signed 2s complement numbers. The multiplier uses a new coding scheme for representing radix-2 signed digits. The coding results in a factor of two reduction in the number of summands used with respect to the modified Booth algorithm. The design has a small number of modular cells and regular routing, making it suitable for automatic synthesis of larger data-width multipliers. In addition, the row-based redundant binary adder tree is an ideal structure for high-throughput applications.

Video coding for HDTV systems

The adoption of MPEG-2 (Motion Pictures Experts Group) by the FCC as the HDTV video compression and transport methodologies laid the foundation for merging multimedia, broadcasting and telecommunication applications. The MPEG-2 video standard, frozen in Nov. 93, supports data rates above 10 Mpbs, real-time transmission, and progressive and interlaced scan sources. This tutorial describes the basic components of an MPEG-2 based HDTV compression system including video formats, color space transformation and decimation, motion estimation and compensation, discrete cosine transform, and variable-length coding. The frame-based and field-based motion estimation schemes required for interlaced scan sources are described in detail. Also discussed is the specific profile and level targeting HDTV application in the MPEG-2 standard.<<ETX>>

High-performance hardware for function generation

High speed elementary function generation is crucial to the performance of many DSP applications. The paper presents an interpolator architecture for generating elementary functions based on an optimal trade off between the use of memory modules and computational circuits. The architecture uses one third less memory than alternative schemes while incurring no time penalty and minimal additional circuit. The pipelined design has a throughput of generating one functional value per clock cycle, and a latency of two clock cycles.

4:1 checkerboard algorithm for motion estimation

Motion-compensated prediction is a key technique for achieving high compression performance for a video sequence. Exhaustive search produces the best predictor block but requires intensive computation and expensive hardware. This paper presents a 4:1 checker-board algorithm that reduces the computational complexity of exhaustive search by a factor of 8 while maintaining similar video quality. The algorithm subsamples block pixels by four to one, wand subsamples search locations by two to one. The resulting architecture is simple and scalable, and is suitable for real-time encoding.

Work in progress-recruiting Hispanic students into computing through community service learning

The San José State University College of Engineering implemented a new approach for recruiting Hispanic students into computing disciplines and careers through the Hispanic Computer Brigade (HCB) initiative. To support the HCB, we received funding from the National Science Foundation (NSF) for a one-year pilot program for Hispanic students from the San Jose East Side Union High School District. The high school students began the program with a summer camp in Summer 2009, continued to learn and engage computing throughout the 2009–2010 academic year with community service learning, and will end with a local event where students will share their computing projects with high school faculty, SJSU faculty, parents/guardians, and the community. Students are learning computer and programming skills and processes in weekly meetings with the help of high school teachers and San Jose State University student mentors.