Donald L. Hung

Digital hardware realization of a recurrent neural network for solving the assignment problem

Abstract The digital hardware realization of a recurrent neural network for solving the assignment problem is presented. The design is based on an analog neural network and is mapped to a one-dimensional systolic array for parallel processing. The processing elements are connected with a ring topology that reduces the overhead in controlling the pipeline. The design was simplified by exploiting regularities in the data to eliminate the need for multipliers and dividers in hardware implementation. The results of implementation and verification based on field programmable gate array device show the feasibility of the digital neural network approach to the assignment problem.

Design of a hardware accelerator for real-time moment computation: a wavefront away approach

In image processing, pattern recognition, and computer vision, one of the most powerful techniques for feature extraction is to use moments. Real-time applications of this method, however, have been prohibited due to the intensive computation encountered in calculating the moments. One solution to this problem is to adopt specially designed hardware accelerators. This paper describes, from a practical standpoint, the design of a custom hardware accelerator for speeding up the moment computation. The design of the core functional units and the design of the overall system based on a wavefront array architecture are discussed. The moment accelerator can be easily configured into different sizes to meet diverse application requirements cost effectively. Testing results based on implementation using field-programmable gate array devices show that, at an affordable cost, the proposed hardware accelerator can deliver real-time speeds for moment computation. Elimination of this computational bottleneck makes it possible to use moments-based features in real-time industrial applications.

Breast Cancer Classification Using Fuzzy Central Moments

Breast cancer continues to be one of the most deadly diseases among American women, which is the second leading cause of cancer-related mortality among American women. Currently there are more than 50 million women over the age of 40 at risk of breast cancer and approximately 144,000 new cases of breast cancer are expected each year in the United States. One out of eight women will develop breast cancer at some point during her lifetime in this country [1,2]. Because of the high incidence of breast cancer, any improvement in the process of diagnosing the disease may have a significant impact on saving lives and cutting costs in the health care system. Since the cause of breast cancer remains unknown and the earlier stage tumors can be more easily and less expensively treated, early detection is the key to breast cancer control. Mammography has proven to be the most reliable method and the major diagnosis means for detecting and classifying breast cancer in the early stage. Studies have shown a decrease in both severe breast cancer and mortality in women who undergo regular mammographic screens [3].

Design of a configurable accelerator for moment computation

The method of moments is one of the most powerful techniques for image analysis. However, real-time applications of this method have been prohibited due to the computational intensity in calculating the moments. This paper presents a novel configurable hardware accelerator for expediting the moment computation. The fundamental building block of the proposed accelerator is a custom-designed floating-point moment processing element (MPE). Running at 75 MHz, the MPE can provide a 12X speedup over a 166 MHz TMS320C6701 digital signal processor. On top of this, a linear performance boost can be obtained by connecting up to eight MPEs into a one-dimensional (1-D) array.

A FPGA-based custom computing system for solving the assignment problem

The assignment problem is a classical combinatorial optimization problem arising in numerous design and planning contexts. Solving an assignment problem of large scale is computationally intensive and time consuming. The paper discusses the development of an FPGA based custom computing system that can accelerate the computation by exploiting the intrinsic parallelism of a recently proposed recurrent neural network for solving the assignment problem. The theoretical background of this work has been discussed in other papers. The digital realization of the system, including architecture, design, FPGA implementation and verification are discussed.

A reconfigurable hardware accelerator for moment computation

In image processing, moment-invariant is one of the most useful methods for feature extraction. However, real-time applications of this method have been prohibited due to the intensive computation required in calculating the moments of an image. This paper describes a hardware solution to this problem.

Pilot study of college student laptop usage for energy efficiency

The energy consumption of consumer electronics has skyrocketed. According to IEA (International Energy Agency), it will triple over the next two decades, reaching a level equivalent to the present total home electricity consumption of the U.S. and Japan combined. Therefore, improving the energy efficiency of these devices has become critical. Our project, called ugreen, seeks to motivate power consumption awareness and behavioral change among laptop computer users via human-computer interaction (HCI) feedback mechanisms with college students as the initial target group. We have chosen college students because they are avid laptop users with 87.7% of them reporting laptop ownership [1], and user behaviors play an important role in the total laptop system power consumption [2].

Teaching SoC-oriented computer design course

As SoC becomes the mainstream design approach for embedded computing systems, a challenging task for the education community is to update the traditional curriculum to reflect the changes in technology. This paper reports the authors experience at San Jose State University in teaching a graduate-level computer design course based on the SoC approach. Motivation, scope of the course, teaching approach and outcomes are presented; ongoing activities and future development plans are mentioned in the conclusion part of the paper.

Developing a teaching environment for rapid design and verification of complex digital/computing systems

This paper first discusses the need and difficulties for the education community to establish an environment to teach system-level design and verification, then describes the activities at San Jose State University (Computer Engineering Department) in developing such an environment through a low cost approach. A demo is provided along with the paper.

Architecture and design of a hardware accelerator for efficient 3D object recognition using the LC method

Abstract The linear combination (LC) method is a powerful technique for 3D object recognition. The major computation involved in this method appears in the learning phase, where three sets of simultaneous linear equations must be solved for each observed image. Due to the high computational expense, the learning process is normally conducted off line, and sizes of the linear equation sets are usually kept small at the price of reduced accuracy. To make the LC method suitable for real-time 3D object recognition, the key issue is to expedite the learning process by reducing the time consumed in solving the simultaneous linear equations. To address this issue, we propose a hardware accelerator for solving sets of linear equations based on iterative methods. Using a single accelerator as a co-processor, a linear speedup can be obtained comparing with a single processor running the same type of equation solvers. By connecting multiple accelerators in parallel, computation time can be further reduced by at least an order of magnitude.