Bengt Erik Jonsson

A survey of A/D-Converter performance evolution

This paper presents the performance evolution over time for monolithic ADC implementations reported in scientific publications. The survey is based on an exhaustive search of IEEE journals and conferences central to the field from 1974 to 2010 and thus represents a near-exhaustive survey of reported scientific ADC data. Based on the full set of historical data, empirically observed evolution trends are extracted. The trends are used to predict the state-of-the-art specifications of future ADCs and also form a valuable reference and complement to theoretical performance limits derived in other works.

New A/D converter architectures based on Gray coding

In this paper, we propose the use of Gray codes in algorithmic and pipeline A/D converters. The major advantage is the tolerance to offset errors in circuit realizations compared with traditional A/D converters using binary coding. Both theoretical investigation and system simulation indicate that the Gray code algorithmic and pipeline AID converters are well suited for high-resolution and/or low-distortion applications.

Distortion in sampling

This paper deals with distortion caused by signal-dependent jitter in high-speed sampling of an analog signal. Sampling circuits using MOS switches are analyzed in particular, but the results are applicable to any sampling switch with a signal dependent switch-off threshold. When sampling with MOS switches it is concluded that fully-differential sampling using single-type rather than CMOS switches has the best performance regarding jitter distortion.

Clock-Feedthrough Compensated First-Generation SI Circuitsand Systems

In this paper we discuss the clock-feedthrough problemin switched-current circuits. We present a clock-feedthroughcompensated first-generation SI memory cell that ideally cancelsboth constant and signal-dependent clock-feedthrough. It is shownhow to optimize the memory cell performance according to a generalcost function. Measured total harmonic distortion of the memorycell is less than -65 dB when optimized for low-power. The implementationof a second-order delta-sigma modulator using the presented memorycell is also described. Measurements confirmed a dynamic rangeof 11 bits. All circuits were implemented in a single-poly CMOSprocess.

A dual 3-V 32-MS/s CMOS switched-current ADC for telecommunication applications

The potential for switched-current A/D converters in low-voltage, telecommunication applications with a high level of integration is investigated through a test design. A dual, 3 V, 32 MS/s A/D converter was fabricated in a standard digital 5 V, 0.8 /spl mu/m CMOS process. Fully differential first-generation switched-current circuits with common-mode feedforward are used to implement a 1.5-b/stage pipelined ADC core. Eight time-interleaved ADC cores operating at 4 MS/s are used to achieve a high sample rate. With channel compensation, the measured SFDR is more than 50 dB at 32 MS/s with f/sub in/=1.13 MHz. The ADC-core was measured to have 60.3 dB peak SFDR, 46.5 dB peak SNDR, and approximately 20 MHz input bandwidth. The resolution of the parallel ADC was limited by additional noise and the useful bandwidth was lowered by a fixed-pattern timing error that could not be removed by channel calibration.

Sampling jitter in high-speed SI circuits

Random and signal dependent sampling time uncertainty in high-speed switched-current circuits are analyzed, and comparison with voltage-mode sampling is made. The similarity of the two techniques is shown as well as the fact that the lower voltage swing in switched-current circuits, makes them less sensitive to the signal dependent switch-off time of the sampling switch. Derivations and simulation results showing the effects of clock phase-noise, additive clock driver noise, and signal-dependent sampling time uncertainty are included. Reduction of signal-dependent jitter errors by using fully-differential switched-current sampling is also illustrated.

A 3 V, 10 bit, 6.4 MHz switched-current CMOS A/D converter design

An experimental 6.4 MS/s CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to realize a 1.5-b/stage pipelined architecture. High sampling rate and large input bandwidth were the main design objectives. The complete ADC was simulated using a SPICE level simulator. Performance is verified by analyzing the FFT of 2048 simulated samples. With f/sub in/=3.05 MHz, the simulated SFDR=62.7 dB and SNDR=57 dB. Simulations also indicate more than 6.7 effective number of bits at f/sub in/=15.85 MHz. Thus a high input signal bandwidth is demonstrated. Power dissipation is estimated to be less than 90 mW from a 3.0 V supply. Die area is 2.7 mm/sup 2/ when implemented in a 0.8 /spl mu/m digital CMOS process.

A 3 V switched-current pipelined analog-to-digital converter in a 5 V CMOS process

An experimental A/D converter design is presented. Fully differential first-generation switched-current circuits with common-mode feed-forward were used to implement a 1.5-b/stage pipelined architecture. With a 1.83 MHz input current sampled at 3 MHz, the measured SFDR and SNDR is 60.3 and 46.5 dB respectively. Measurement results are compared with previously reported wide-band switched-current A/D converters. It is seen that, in this work, a very large input bandwidth and a low distortion is demonstrated.

A 3.3-V CMOS Switched-Current Delta-Sigma Modulator

This chapter presents the design of a second-order switched-current delta-sigma modulator having equal first and second integrator output swing. It was implemented using the clock-feedthrough compensated first-generation switched-current circuits described in chapter 4. Experimental results show that the modulator has a small chip area, low supply voltage, and low power dissipation. The measured dynamic range is approximately 11 bits.

A 3-V Wideband CMOS Switched-Current A/D-Converter

The simulated and measured performance of an experimental wideband CMOS A/D converter design is presented in this chapter. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture in order to evaluate the switched-current technique for digital radio applications. With f in = 1.83 MHz, the measured SFDR = 60.3 dB and SNDR = 46.5 dB at f s = 3 MHz. Although this 3 V design was fabricated in a standard digital 5 V, 0.8 μm CMOS process, a high bandwidth was achieved. Since the ADC maintains an SNDR ≥ 40 dB for input frequencies of more than 20 MHz, it has the highest input bandwidth reported for any CMOS switched-current A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared with the measured performance of other wideband switched-current A/D converters and found to be competitive also with respect to area and power efficiency.