Nianxiong Tan

Switched-current delta-sigma A/D converters

Switched-current oversampling A/D converters are the ideal choice for mixed analog/digital design due to their complete compatibility with digital CMOS process and high tolerance to process variation. This paper presents a tutorial discussion on all the aspects of switched-current oversampling A/D converters, including structures, circuits, and practical issues. Three different modulator structures and six different types of switched-current circuits were used with an emphasis on low-voltage operation. Eight 3.3-V oversampling A/D converters were implemented and measured, and another one 1.2-V oversampling A/D converter was also implemented but yet to be measured.

New A/D converter architectures based on Gray coding

In this paper, we propose the use of Gray codes in algorithmic and pipeline A/D converters. The major advantage is the tolerance to offset errors in circuit realizations compared with traditional A/D converters using binary coding. Both theoretical investigation and system simulation indicate that the Gray code algorithmic and pipeline AID converters are well suited for high-resolution and/or low-distortion applications.

Distortion in sampling

This paper deals with distortion caused by signal-dependent jitter in high-speed sampling of an analog signal. Sampling circuits using MOS switches are analyzed in particular, but the results are applicable to any sampling switch with a signal dependent switch-off threshold. When sampling with MOS switches it is concluded that fully-differential sampling using single-type rather than CMOS switches has the best performance regarding jitter distortion.

Clock-Feedthrough Compensated First-Generation SI Circuitsand Systems

In this paper we discuss the clock-feedthrough problemin switched-current circuits. We present a clock-feedthroughcompensated first-generation SI memory cell that ideally cancelsboth constant and signal-dependent clock-feedthrough. It is shownhow to optimize the memory cell performance according to a generalcost function. Measured total harmonic distortion of the memorycell is less than -65 dB when optimized for low-power. The implementationof a second-order delta-sigma modulator using the presented memorycell is also described. Measurements confirmed a dynamic rangeof 11 bits. All circuits were implemented in a single-poly CMOSprocess.

Very Low-Voltage Switched-Current Circuits in Standard Digital CMOS Process

The inherent simplicity of switched-current circuits makes them suitable for low-voltage and very low voltage operation. This paper presents the design of 1.2-V switched-current circuits in a standard digital CMOS process. The core elements are the proposed fully differential SI memory cell and high resolution current quantizer. A delay line and a second-order delta-sigma modulator are implemented and measured. The delay line occupies an active chip area of 0.2 mm2 and dissipates a power of 0.2 mW, and the modulator occupies an active chip area of 0.47 mm2 and dissipates a power of 0.78 mW. The measured total harmonic distortion of the delay line is less than −48 dB with a 60% input modulation index and the measured dynamic range of the modulator is 10 bits.