Benjamin Bishop

A detailed analysis of MediaBench

In this paper, we present a detailed analysis of the MediaBench benchmark suite. MediaBench consists of a number of popular embedded applications for communications and multimedia. MediaBench performance characteristics were examined by running MediaBench under the SimpleScalar simulation environment. Characteristics such as instruction mix, branch prediction accuracy, cache hit rates, memory usage, and integer bit utilization were considered. This information can be of use in designing embedded systems targeted at multimedia applications.

Databus charge recovery: practical considerations

The charge recovery databus is a scheme which reduces energy consumption through the application of adiabatic circuit techniques. A previous work by Khoo et al. (1995) gives a solid theoretical analysis of this scheme, including quantitative data assuming random bus values. We extend this earlier work by presenting a quantitative analysis of the charge recovery databus using 15 benchmarks and 4 high-level bus coding schemes. We show that a very simple implementation of the charge recovery databus is capable of reducing average energy consumption by 28% beyond traditional high-level bus encoding techniques.

The design of a register renaming unit

Register renaming is often used to improve performance in many high-ILP processors. However there is a lack of publications regarding register renaming hardware design. This paper presents a detailed look at one possible implementation of a register renaming unit, as well as some possible optimizations.

A low-energy adaptive bus coding scheme

We have extracted run-time memory access traces from the Mediabench benchmark set. These traces exhibit a high degree of repetition. We propose an adaptive bus coding scheme that will reduce transition activity by exploiting value repetition. For this scheme, we introduce an extra bitline similar to bus-invert coding.

Optimizing the android virtual keyboard: A study of user experience

Virtual keyboards for mobile devices continue to lack the accuracy and efficiency of their mechanical counterparts. The intent of this study is to analyze the effectiveness of various virtual keyboard implementations employing key-resizing strategies on an Android mobile phone. Study participants were asked to type various phrases using three different virtual keyboard implementations in both portrait and landscape orientations. Quantitative results were reported and conclusions were derived to aid in the development and implementation of more efficient virtual keyboard interfaces for mobile devices.

SPARTA: Simulation of Physics on a Real-Time Architecture

In this paper, we discuss hardware acceleration for real-time physical modeling that would allow for realistic virtual environments. Additionally, we propose algorithms and their architectural implementation (SPARTA), which is specifically tuned for real-time use. We expect performance orders of magnitude higher than general-purpose CPUs.

Design of databus charge recovery mechanism

We present a design for a charge recovery databus. Previous works have laid the groundwork for our design, presenting the theory that would make adiabatic circuit techniques useful. During a shorting period, the charge is transferred from the falling bit-lines to precharge the rising bit-lines while both the sender and the receiver are off. We simulate this 8-bit charge recovery bus with data based on realistic benchmarks. The power savings average 20% over typical on-chip and off-chip bus capacitances. The savings increase with larger bus capacitances and longer shorting times. The overhead of the control circuitry is estimated at 3.6% of the total power consumption.

Three dimensional graphics algorithms on the Micro-Grain Array Processor. II

High performance graphics subsystems play a critical role in many computer systems, but result in high priced systems that often still fall short of the required graphics performance. The root of the problem lies in the complex graphics algorithms that require large amounts of object data to be manipulated with high throughput, such as what is required for ray tracing. This has resulted in complex, real-time 3D graphics to be limited to high-end systems. In this paper, we present a library of 3D graphics algorithms that have been mapped to the Micro-Grain Array Processor (MGAP), an inexpensive and versatile SIMD processing board capable of fitting in a typical workstation. Our results show that the MGAP can produce comparable data throughput as more costly graphics subsystems, while maintaining the flexibility of being a general purpose parallel machine.

HELLAS: a specialized architecture for interactive deformable object modeling

Applications involving interactive modeling of deformable objects require highly iterative, floating-point intensive numerical simulations. As the complexity of these models increases, the computational power required for their simulation quickly grows beyond the capabilities of current general purpose systems. In this paper, we present the design of a low--cost, high--performance, specialized architecture to accelerate these simulations. Our aim is to use such specialized hardware to allow complex interactive physical modeling even on consumer-grade PCs. In this paper, we present details of the target algorithms, the HELLAS architecture, simulation results and lessons learned from our implementation.

Specialized hardware for deformable object modeling

Deformable object modeling is a technology that will enable a broad range of new applications. Unfortunately, current techniques are far from being able to offer interactive performance for realistic scenes. We examine the idea of using low-cost highly specialized hardware in order to accelerate deformable object modeling. Details are presented regarding two generations of such experimental systems.