Thomas P. Kelliher

ELM-a fast addition algorithm discovered by a program

A new addition algorithm, ELM, is presented. This algorithm makes use of a tree of simple processors and requires O(log n) time, where n is the number of bits in the augend and addend. The sum itself is computed in one pass through the tree. This algorithm was discovered by a VLSI CAD tool, FACTOR, developed for use in synthesizing CMOS VLSI circuits. >

A detailed analysis of MediaBench

In this paper, we present a detailed analysis of the MediaBench benchmark suite. MediaBench consists of a number of popular embedded applications for communications and multimedia. MediaBench performance characteristics were examined by running MediaBench under the SimpleScalar simulation environment. Characteristics such as instruction mix, branch prediction accuracy, cache hit rates, memory usage, and integer bit utilization were considered. This information can be of use in designing embedded systems targeted at multimedia applications.

The design of a register renaming unit

Register renaming is often used to improve performance in many high-ILP processors. However there is a lack of publications regarding register renaming hardware design. This paper presents a detailed look at one possible implementation of a register renaming unit, as well as some possible optimizations.

SPARTA: Simulation of Physics on a Real-Time Architecture

In this paper, we discuss hardware acceleration for real-time physical modeling that would allow for realistic virtual environments. Additionally, we propose algorithms and their architectural implementation (SPARTA), which is specifically tuned for real-time use. We expect performance orders of magnitude higher than general-purpose CPUs.

Simultaneous speech segmentation and phoneme recognition using dynamic programming

In this paper a dynamic programming algorithm for simultaneous speech segmentation and phoneme recognition is presented. Given a sequence of samples of an unknown speech pattern and a library of phonemes, this algorithm finds the best phonological match and, with a backtracking step, identifies the phoneme boundaries. This approach is different from a traditional two step process whereby first the phoneme boundaries are determined locally and then speech recognition is performed. Its advantage over the two step process is that incorrect phoneme boundaries due to slurring or sudden changes in the speech are reduced. Unlike other dynamic programming algorithms, it does not lend itself to systolic wavefront processing, hence an alternate parallel algorithm is presented.

The arithmetic cube II: a second generation VLSI DSP processor

A description is given of the synthesis, design, and simulation of the arithmetic cube II, a second-generation, high-performance digital signal processing architecture. The architecture implements the so-called small-n algorithms. The authors are currently building a CMOS prototype system which should be capable of computing a 1024 point complex DFT in 410 mu s.<<ETX>>

HELLAS: a specialized architecture for interactive deformable object modeling

Applications involving interactive modeling of deformable objects require highly iterative, floating-point intensive numerical simulations. As the complexity of these models increases, the computational power required for their simulation quickly grows beyond the capabilities of current general purpose systems. In this paper, we present the design of a low--cost, high--performance, specialized architecture to accelerate these simulations. Our aim is to use such specialized hardware to allow complex interactive physical modeling even on consumer-grade PCs. In this paper, we present details of the target algorithms, the HELLAS architecture, simulation results and lessons learned from our implementation.

Specialized hardware for deformable object modeling

Deformable object modeling is a technology that will enable a broad range of new applications. Unfortunately, current techniques are far from being able to offer interactive performance for realistic scenes. We examine the idea of using low-cost highly specialized hardware in order to accelerate deformable object modeling. Details are presented regarding two generations of such experimental systems.

Hardware/software co-design for real-time physical modeling

Physical modeling of a mass-spring system allows for realistic object motion and deformation in a virtual environment. Previous work in this type of physical modeling relies on general-purpose hardware, and cannot offer the performance necessary for real-time human-machine interaction. In this paper, we consider the co-design of software and hardware in order to achieve real-time physical modeling.

The MGAP family of processor arrays

The Micro-Grain Array Processor (MGAP) is a family of massively parallel SIMD arrays of fine grain processing elements powerful enough to perform complex signal and image processing algorithms in real time. The MGAP was also designed to be compact enough to conveniently fit as an add-on board to a standard workstation at a fraction of the development cost of other comparable parallel machines. In this paper we update the status of the MGAP-2 which became operational in October 1996, and present a comparison of the MGAP-1 and the MGAP-2. We also give performance comparisons of the two designs through three popular image/video compression algorithms: the Discrete Cosine Transform, Motion Estimation, and Fractal Compression.