Benjamin G. Lee

Optical 4x4 hitless slicon router for optical networks-on-chip (NoC)

We demonstrate here a spatially non-blocking optical 4x4 router with a footprint of 0.07 mm(2) for use in future integrated photonic interconnection networks. The device is dynamically switched using thermo-optically tuned silicon microring resonators with a wavelength shift to power ratio of 0.25nm/mW. The design can route four optical inputs to four outputs with individual bandwidths of up to 38.5 GHz. All tested configurations successfully routed a single-wavelength laser and provided a maximum extinction ratio larger than 20 dB.

All-Optical Comb Switch for Multiwavelength Message Routing in Silicon Photonic Networks

Simultaneous all-optical switching of 20 continuous-wave wavelength channels is achieved in a microring resonator-based silicon broadband 12 comb switch. Moreover, single-channel power penalty measurements are performed during active operation of the switch at both the through and the drop output ports. A statistical characterization of the drop-port insertion losses and extinction ratios of both ports shows broad spectral uniformity, and bit-error-rate measurements during passive operation indicate a negligible increase in signal degradation as the number of wavelength channels exiting the drop port are scaled from one to 16, with peak powers of 6 dBm per channel. A high-speed broadband switching device, such as the one described here, is a crucial element for the deployment of interconnection networks based on silicon photonic integrated circuits.

Photonic NoC for DMA Communications in Chip Multiprocessors

As multicore architectures prevail in modern high- performance processor chip design, the communications bottleneck has begun to penetrate on-chip interconnects. With vastly growing numbers of cores and on-chip computation, a high-bandwidth, low-latency, and, perhaps most importantly, low-power communication infrastructure is critically required for next generation chip multiprocessors. Recent remarkable advances in silicon photonics and the integration of photonic elements with standard CMOS processes suggest the use of photonic networks-on-chip. In this paper we review the previously proposed architecture of a hybrid electronic/photonic NoC. We improve the former internally blocking switches by designing a non-blocking photonic switch, and we estimate the optical loss budget and area requirements of a practical NoC implementation based on the new switches. Additionally, we tackle one of the key performance challenges: the latency associated with setting-up photonic paths. Simulations show that the technique suggested can substantially reduce the latency and increase the effective bandwidth. Finally, we consider the DMA communication model in the context of the photonic network and evaluate the optimal DMA block size.

Ultrahigh-Bandwidth Silicon Photonic Nanowire Waveguides for On-Chip Networks

An investigation of signal integrity in silicon photonic nanowire waveguides is performed for wavelength-division-multiplexed optical signals. First, we demonstrate the feasibility of ultrahigh-bandwidth integrated photonic networks by transmitting a 1.28-Tb/s data stream (32 wavelengths times 40-Gb/s) through a 5-cm-long silicon wire. Next, the crosstalk induced in the highly confined waveguide is evaluated, while varying the number of wavelength channels, with bit-error-rate measurements at 10 Gb/s per channel. The power penalty of a 24-channel signal is 3.3 dB, while the power penalty of a single-channel signal is 0.6 dB. Finally, single-channel power penalty measurements are taken over a wide range of input powers and indicate negligible change for launch powers of up to 7 dBm.

The Data Vortex Optical Packet Switched Interconnection Network

A complete review of the data vortex optical packet switched (OPS) interconnection network architecture is presented. The distributed multistage network topology is based on a banyan structure and incorporates a deflection routing scheme ideally suited for implementation with optical components. An implemented 12-port system prototype employs broadband semiconductor optical amplifier switching nodes and is capable of successfully routing multichannel wavelength-division multiplexing packets while maintaining practically error-free signal integrity (BER < 10-12) with median latencies of 110 ns. Packet contentions are resolved without the use of optical buffers via a distributed deflection routing control scheme. The entire payload path in the optical domain exhibits a capacity of nearly 1 Tb/s. Further experimental measurements investigate the OPS interconnection networks flexibility and robustness in terms of optical power dynamic range and network timing. Subsequent experimental investigations support the physical layer scalability of the implemented architecture and serve to substantiate the merits of the data vortex OPS network architectural paradigm. Finally, modified design considerations that aim to increase the network throughput and device-level performance are presented.

Demonstration of Broadband Wavelength Conversion at 40 Gb/s in Silicon Waveguides

We present ultra-broadband wavelength conversion in silicon photonic waveguides at a data rate of 40 Gb/s. The dispersion-engineered device demonstrates a conversion bandwidth spanning the entire S-, C-, and L-bands of the ITU grid. Using a continuous-wave C-band pump, an input signal of wavelength 1513.7 nm is up-converted across nearly 50 nm at a data rate of 40 Gb/s, and bit-error-rate measurements are performed on the converted signal.

High-Performance Modulators and Switches for Silicon Photonic Networks-on-Chip

The stringent on- and off-chip communications demands of future-generation chip multiprocessors require innovative and potentially disruptive technology solutions, such as chip-scale photonic transmission systems. A space-switched, wavelength-parallel photonic network-on-chip has been shown to equip users with high-bandwidth, low-latency links in an energy-efficient manner. Here, experimental measurements on fabricated silicon photonic devices verify a large set of the components needed to construct these networks. The proposed system architecture is reviewed to motivate the demanding performance requirements of the components. Then, systems-level investigations are delineated for multiwavelength electrooptic modulators and photonic switching elements arranged in 1 × 2, 2 × 2, and 4 × 4 formations. Compact (~10 ¿m), high-speed (4 Gb/s) modulators, having a large degree of channel scalability (four channels demonstrated), are demonstrated with excellent data integrity (bit error rates (BERs) <10-12). Meanwhile, switches are shown to transfer extensive throughput bandwidths (250 Gb/s) with fast switching speeds (<1 ns) and sufficient extinction ratios (>10 dB). Data integrity is also verified for the switches (BERs < 10-12) with power penalty measurements amid dynamic operation. These network component demonstrations verify the feasibility of the proposed system architecture, while previous works have verified its efficacy.

Broadband Operation of Nanophotonic Router for Silicon Photonic Networks-on-Chip

A nonblocking four-port bidirectional multiwavelength message router for use in photonic network-on-chip (NoC) architectures implementing two-dimensional mesh or torus topologies is fully characterized with bit-error-rate measurements and eye diagrams using three wavelength-parallel 10-Gb/s channels. The experiments demonstrate the feasibility of using this advanced switching subsystem within dynamically routed multiwavelength photonic NoCs.

Design Exploration of Optical Interconnection Networks for Chip Multiprocessors

The network-on-chip (NoC) paradigm has emerged as a promising solution for providing connectivity among the increasing number of cores that get integrated into both systems-on chip (SoC) and chip multiprocessors (CMP). In future high performance CMPs, however, the high bandwidth requirements will not be adequately provided by electronic NoCs without dissipating large amounts of power. Previously, we have made the case for the photonic NoC as a unique interconnect solution for delivering scalable bandwidth-per-watt performance that surpasses equivalent electronic NoCs. Building on this work, we study the adoption of photonic communication for CMPs and we present three main contributions: (1) we propose two nonblocking topologies for photonic NoC designs and we assess both qualitatively and quantitatively the pros and cons that they offer with respect to the original (blocking) topology, (2) we show how a photonic NoC is better suited for a CMP made of complex multi-threaded cores, and (3) we present the first simulation based assessment of the benefits of using a photonic NoC for a real application, i.e. computing a large FFT.

Wavelength multicasting in silicon photonic nanowires

We demonstrate a scalable, energy-efficient, and pragmatic method for high-bandwidth wavelength multicasting using FWM in silicon photonic nanowires. We experimentally validate up to a sixteen-way multicast of 40-Gb/s NRZ data using spectral and temporal responses, and evaluate the resulting data integrity degradation using BER measurements and power penalty performance metrics. We further examine the impact of this wavelength multicasting scalability on conversion efficiency. Finally, we experimentally evaluate up to a three-way multicast of 160-Gb/s pulsed-RZ data using spectral and temporal responses, representing the first on-chip wavelength multicasting of pulsed-RZ data.