Keren Bergman

Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors

The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die. We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intra-chip and off-chip communication on the overall power budget. A photonic interconnection network can deliver higher bandwidth and lower latencies with significantly lower power dissipation. We explain why on-chip photonic communication has recently become a feasible opportunity and explore the challenges that need to be addressed to realize its implementation. We introduce a novel hybrid micro-architecture for NoCs combining a broadband photonic circuit-switched network with an electronic overlay packet-switched control network. We address the critical design issues including: topology, routing algorithms, deadlock avoidance, and path-setup/tear-down procedures. We present experimental results obtained with POINTS, an event-driven simulator specifically developed to analyze the proposed idea, as well as a comparative power analysis of a photonic versus an electronic NoC. Overall, these results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs.

Characterization of photodamage to Escherichia coli in optical traps.

Optical tweezers (infrared laser-based optical traps) have emerged as a powerful tool in molecular and cell biology. However, their usefulness has been limited, particularly in vivo, by the potential for damage to specimens resulting from the trapping laser. Relatively little is known about the origin of this phenomenon. Here we employed a wavelength-tunable optical trap in which the microscope objective transmission was fully characterized throughout the near infrared, in conjunction with a sensitive, rotating bacterial cell assay. Single cells of Escherichia coli were tethered to a glass coverslip by means of a single flagellum: such cells rotate at rates proportional to their transmembrane proton potential (Manson et al.,1980. J. Mol. Biol. 138:541-561). Monitoring the rotation rates of cells subjected to laser illumination permits a rapid and quantitative measure of their metabolic state. Employing this assay, we characterized photodamage throughout the near-infrared region favored for optical trapping (790-1064 nm). The action spectrum for photodamage exhibits minima at 830 and 970 nm, and maxima at 870 and 930 nm. Damage was reduced to background levels under anaerobic conditions, implicating oxygen in the photodamage pathway. The intensity dependence for photodamage was linear, supporting a single-photon process. These findings may help guide the selection of lasers and experimental protocols best suited for optical trapping work.

Optical 4x4 hitless slicon router for optical networks-on-chip (NoC)

We demonstrate here a spatially non-blocking optical 4x4 router with a footprint of 0.07 mm(2) for use in future integrated photonic interconnection networks. The device is dynamically switched using thermo-optically tuned silicon microring resonators with a wavelength shift to power ratio of 0.25nm/mW. The design can route four optical inputs to four outputs with individual bandwidths of up to 38.5 GHz. All tested configurations successfully routed a single-wavelength laser and provided a maximum extinction ratio larger than 20 dB.

On the Design of a Photonic Network-on-Chip

Recent remarkable advances in nanoscale silicon-photonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the unique capabilities of optical technologies in the on-chip communications infrastructure. Based on these nano-photonic building blocks, we consider a photonic network-on-chip architecture designed to exploit the enormous transmission bandwidths, low latencies, and low power dissipation enabled by data exchange in the optical domain. The novel architectural approach employs a broadband photonic circuit-switched network driven in a distributed fashion by an electronic overlay control network which is also used for independent exchange of short messages. We address the critical network design issues for insertion in chip multiprocessors (CMP) applications, including topology, routing algorithms, path-setup and tear-down procedures, and deadlock avoidance. Simulations show that this class of photonic networks-on-chip offers a significant leap in the performance for CMP intrachip communication systems delivering low-latencies and ultra-high throughputs per core while consuming minimal power

All-Optical Comb Switch for Multiwavelength Message Routing in Silicon Photonic Networks

Simultaneous all-optical switching of 20 continuous-wave wavelength channels is achieved in a microring resonator-based silicon broadband 12 comb switch. Moreover, single-channel power penalty measurements are performed during active operation of the switch at both the through and the drop output ports. A statistical characterization of the drop-port insertion losses and extinction ratios of both ports shows broad spectral uniformity, and bit-error-rate measurements during passive operation indicate a negligible increase in signal degradation as the number of wavelength channels exiting the drop port are scaled from one to 16, with peak powers of 6 dBm per channel. A high-speed broadband switching device, such as the one described here, is a crucial element for the deployment of interconnection networks based on silicon photonic integrated circuits.

Optical interconnection networks for high-performance computing systems

Enabled by silicon photonic technology, optical interconnection networks have the potential to be a key disruptive technology in computing and communication industries. The enduring pursuit of performance gains in computing, combined with stringent power constraints, has fostered the ever-growing computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally different communication approaches. Chip-scale photonic interconnection networks, enabled by high-performance silicon photonic devices, offer unprecedented bandwidth scalability with reduced power consumption. We demonstrate that the silicon photonic platforms have already produced all the high-performance photonic devices required to realize these types of networks. Through extensive empirical characterization in much of our work, we demonstrate such feasibility of waveguides, modulators, switches and photodetectors. We also demonstrate systems that simultaneously combine many functionalities to achieve more complex building blocks. We propose novel silicon photonic devices, subsystems, network topologies and architectures to enable unprecedented performance of these photonic interconnection networks. Furthermore, the advantages of photonic interconnection networks extend far beyond the chip, offering advanced communication environments for memory systems, high-performance computing systems, and data centers.

A fully implemented 12 /spl times/ 12 data vortex optical packet switching interconnection network

A fully functional optical packet switching (OPS) interconnection network based on the data vortex architecture is presented. The photonic switching fabric uniquely capitalizes on the enormous bandwidth advantage of wavelength division multiplexing (WDM) wavelength parallelism while delivering minimal packet transit latency. Utilizing semiconductor optical amplifier (SOA)-based switching nodes and conventional fiber-optic technology, the 12-port system exhibits a capacity of nearly 1 Tb/s. Optical packets containing an eight-wavelength WDM payload with 10 Gb/s per wavelength are routed successfully to all 12 ports while maintaining a bit error rate (BER) of 10/sup -12/ or better. Median port-to-port latencies of 110 ns are achieved with a distributed deflection routing network that resolves packet contention on-the-fly without the use of optical buffers and maintains the entire payload path in the optical domain.

Photonic NoC for DMA Communications in Chip Multiprocessors

As multicore architectures prevail in modern high- performance processor chip design, the communications bottleneck has begun to penetrate on-chip interconnects. With vastly growing numbers of cores and on-chip computation, a high-bandwidth, low-latency, and, perhaps most importantly, low-power communication infrastructure is critically required for next generation chip multiprocessors. Recent remarkable advances in silicon photonics and the integration of photonic elements with standard CMOS processes suggest the use of photonic networks-on-chip. In this paper we review the previously proposed architecture of a hybrid electronic/photonic NoC. We improve the former internally blocking switches by designing a non-blocking photonic switch, and we estimate the optical loss budget and area requirements of a practical NoC implementation based on the new switches. Additionally, we tackle one of the key performance challenges: the latency associated with setting-up photonic paths. Simulations show that the technique suggested can substantially reduce the latency and increase the effective bandwidth. Finally, we consider the DMA communication model in the context of the photonic network and evaluate the optimal DMA block size.

PhoenixSim: a simulator for physical-layer analysis of chip-scale photonic interconnection networks

Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power efficient communications both on- and off-chip. Since optical devices are fundamentally different from conventional electronic interconnect technologies, new design methodologies and tools are required to exploit the potential performance benefits in a manner that accurately incorporates the physically different behavior of photonics. We introduce PhoenixSim, a simulation environment for modeling computer systems that incorporates silicon nanophotonic devices as interconnection building blocks. PhoenixSim has been developed as a cross-discipline platform for studying photonic interconnects at both the physical-layer level and at the architectural and system levels. The broad scope at which modeled systems can be analyzed with PhoenixSim provides users with detailed information into the physical feasibility of the implementation, as well as the network and system performance. Here, we describe details about the implementation and methodology of the simulator, and present two case studies of silicon nanophotonic-based networks-on-chip.

Ultrahigh-Bandwidth Silicon Photonic Nanowire Waveguides for On-Chip Networks

An investigation of signal integrity in silicon photonic nanowire waveguides is performed for wavelength-division-multiplexed optical signals. First, we demonstrate the feasibility of ultrahigh-bandwidth integrated photonic networks by transmitting a 1.28-Tb/s data stream (32 wavelengths times 40-Gb/s) through a 5-cm-long silicon wire. Next, the crosstalk induced in the highly confined waveguide is evaluated, while varying the number of wavelength channels, with bit-error-rate measurements at 10 Gb/s per channel. The power penalty of a 24-channel signal is 3.3 dB, while the power penalty of a single-channel signal is 0.6 dB. Finally, single-channel power penalty measurements are taken over a wide range of input powers and indicate negligible change for launch powers of up to 7 dBm.