Benjamin L. Amey

Effect of Stress-Induced Degradation in LDMOS

Low-frequency noise in double reduced-surface-field lateral-double-diffused-MOS devices has been measured, and the effect of dc stressing is analyzed. The noise components contributing from the extended drain regions under the gate and field oxides were differentiated from the channel noise by a series of experimental and analytical techniques. The effect of voltage stressing on each noise component was investigated. Trapped-charge carrier fluctuations due to Si/SiO2 interface traps in the overlap region in the extended drain as well as in the channel were found to be the dominant source of noise. The bulk resistance fluctuations in the extended drain region under the field oxide were found to be insignificant. High-voltage stressing caused an increase in the interface traps, thus increasing both the extended drain overlap resistance and the noise.

\hbox{1}/f

A physics-based model has been implemented to describe the low-frequency noise behavior in differently processed reduced-surface-field lateral double-diffused MOS devices. The developed model is based upon the correlated carrier number and the mobility fluctuation theory known as the unified model but has been modified to account for the fluctuations in the extended drain and the channel. Unlike the unified 1/f noise model, nonuniform trap distribution has been taken into account with respect to position in the gate oxide and band-gap energy. The effect of stress on dc and noise characteristics has been investigated. Individual resistance and noise components in the channel and in the extended drain regions under the gate and field oxides are evaluated as a function of stress duration. The model is experimentally verified to identify the physical mechanisms for degradation due to stressing.

Noise Characteristics

1/f noise analysis is implemented as a quantitative measure for the dielectric/silicon interface related reliability and degradation in RESURF lateral double-diffused MOS transistors. The effect of DC stress on 1/f noise performance as well as on the location of stress induced degradation have been investigated with respect to stressing time in differently processed low and medium voltage LDMOS. The distribution of traps has been extracted spatially into the oxide and as a function of band-gap energy. The effect of LDMOS drift length to noise degradation has been studied.

A Physics-Based Analytical

Low frequency noise (LFN) characteristics of high voltage double reduced-surface-field LDMOS with SiO2 as gate dielectric is investigated and the effect of DC stressing has been observed. It has been found that the LDMOS does not follow typical noise behavior of ordinary MOSFETs as extended drain attributes a significant role at higher gate overdrive voltages. Here, separation of the overall measured noise components to three distinct regions is proposed: the channel, the resistive region under the gate oxide and that under the field oxide layer. Induced and inherent noise components coming from the extended drain region under the gate and field oxides are separated from the channel noise by performing noise measurements in DNWell standalone resistors.

\hbox{1}/f

1/f noise observed on differently processed high-power, RESURF LDMOS transistors has been correlated with degradation in the drain current and transconductance induced by DC stressing. The effects of stressing are analyzed on individual resistance and noise components in the channel and in the extended drain regions under the gate and field oxides. It has been found that the LDMOS does not follow conventional CMOS noise models due to asymmetric extended drain. A physical model has been derived for the fluctuations in such devices in the lights of Unified 1/f Noise Model. The increase in 1/f noise was found to emerge earlier and in a more pronounced manner in the noise components compared to degradation observed in DC parameters. Such severe noise degradation directly impacts the dielectric-Si interface quality and reliability and eventually affects the device lifetime.

Noise Model for RESURF LDMOS Transistors

In some systems, it is necessary to turn on a low side driver when the load is properly connected to a power supply, even if the normal gate drive power supply is off or disconnected. This necessitates deriving the gate supply voltage for the output device from its own drain voltage. A current mirror method of this drain powered gate drive is explained including theory and simulation. Several additional features possible with the gate drive are also explained. Finally, results are compared for two recent BiCMOS/DMOS (BCD) processes.