Sameer Pendharkar

A Rugged LDMOS for LBC5 Technology

This paper presents a new method of enhancing the SOA of n-channel Ldmos transistors. Attention is focused on those applications where “Electrical SOA” is important and where the power pulse time is typically a few µs or less. Typical applications include gate drives, H-bridge commutation, and self-protection against ESD pulses.

SCR-LDMOS. A novel LDMOS device with ESD robustness

A novel lateral power device structure with a very high degree of ESD (electrostatic discharge) robustness is presented. This device called the SCR-LDMOS is a modification of the lateral LDMOSFET with good on state and blocking characteristics.

Lateral thinking about power devices (LDMOS)

BiCMOS Power technology LDMOS are reviewed with respect to category and structure definition and briefly as to how the structures relate to figure of merit performance. Stepped gate oxide devices are introduced making use of popular dual gate technologies and exhibit improved R/sub sp/ vs. BV performance of up to 30% at low V/sub gs/ without sacrifice of BV. Production use of thick copper plated bussing up to 25 /spl mu/m thick with R/sub sh/=0.8 m/spl Omega//sq is revealed for power, enabling up to 40% efficiency improvement on LDMOS power transistors.

Electrothermal simulations in punchthrough and nonpunchthrough IGBT's

The performance of 1200 V punchthrough (PT) and nonpunchthrough (NPT) insulated gate bipolar transistors (IGBTs) is studied in detail under unclamped inductive switching (UIS) and short circuit (SC) conditions. The need for a good physics based simulator to carry out a reliability study is pointed out in the paper. Using such a finite element-based device and circuit simulator it is shown that NPT-IGBTs show a much better performance than PT-IGBTs under UIS condition. It is also shown that an NPT device has a better short circuit withstanding capability than a PT device due to the structural differences between the two devices. As there is a huge power loss within the device during these operating conditions, device self-heating is expected to have a significant impact on device characteristics. Electrothermal simulations are used to study device self-heating and it is shown that it significantly influences device performance under SC operation whereas self-heating influences the UIS performance of only the PT device with little effect on the NPT device. The study is validated by an experimental study of short circuit failure of PT IGBTs.

Short and long-term safe operating area considerations in LDMOS transistors

Lateral DMOS transistors are widely used in mixed-signal IC circuit designs, particularly where power handling is important. This paper views the LDMOS from a power-handling perspective, considering both design and characterization aspects. The complex nature of the LDMOS safe operating area (SOA) can be dealt with by considering long-term and short-term operating conditions. Long-term conditions are covered by a hot carrier SOA, and short-term conditions are further sub-divided into electrical SOA and thermal SOA. Characterization examples of the various kinds of SOA are given.

Avalanche-induced thermal instability in Ldmos transistors

Safe operating area limits for large Ldmos are shown to be due to a thermal instability mechanism initiated by avalanche generated carriers which turn-on the parasitic bipolar transistor. An analytic model is described and is shown to agree well with experimental data.

Physics-Based Analytical Model for HCS Degradation in STI-LDMOS Transistors

A physics-based analytical model for the on-resistance in the linear transport regime and its application as an alternative tool for the investigation of the hot-carrier stress degradation in shallow-trench-isolation-based laterally diffused MOS devices are presented. The extraction of the model and its validation by comparison with experimental and TCAD data are reported. A thorough investigation of the degradation under low- and high-gate stress biases, corresponding to saturation and impact-ionization regimes, is carried out to gain an insight on the overall bias and temperature dependences of the parameter drifts.

16-60 V rated LDMOS show advanced performance in a 0.72 /spl mu/m evolution BiCMOS power technology

In this work, performance advances are featured for new and improved multi voltage rated (16 V to 60 V) LDMOS. Performance improvements were achieved by leveraging off of (1) an optimized off-set, photo aligned, coimplanted double-diffused well (DWL), (2) two n-type dopings in the drift region, and (3) shrink from 1.0 /spl mu/m to 0.72 /spl mu/m. The R/sub sp/ vs. BV/sub dss/ trend for these devices is the best reported to date for conventional lateral technology: @V/sub gs/=12.75 V (3 MV/cm) R/sub sp/=0.95 m/spl Omega/ cm/sup 2/, BV=69.3 V; R/sub sp/=0.68 m/spl Omega/ cm/sup 2/, BV=50.0 V; R/sub sp/=0.45 m/spl Omega/ cm/sup 2/, BV=33.0 V; R/sub sp/=0.36 m/spl Omega/ cm/sup 2/, BV=19.0 V; for 60, 40, 25, and 16 V rated conventional LDMOS devices.

Analysis of high current breakdown and UIS behavior of resurf LDMOS (RLDMOS) devices

This work analyzes unclamped inductive switching (UIS) behavior of two types of 40 V resurf (reduced surface field) lateral diffused MOSFETs (RLDMOSFETs). It is shown that the addition of a deep buffer implant region on the drain side of the device increases the snap-back current limit as well as UIS robustness. It is also shown, using 2D simulation, that the failure current limit under UIS conditions is not the same as the current at which the parasitic BJT turns on.

Total current collapse in high-voltage GaN MIS-HEMTs induced by Zener trapping

We investigate current collapse in GaN MIS-HEMTs for >600 V operation. Extreme trapping leading to total current collapse has been observed after OFF-state stress at high voltage. We attribute this to high-field tunneling-induced electron trapping (“Zener trapping”) inside the AlGaN barrier or the GaN channel layers. The trapping takes place in a narrow region right under the edge of the outermost field plate in the drain portion of the device. The trapping characteristics are consistent with those responsible for the yellow luminescence band in GaN or AlGaN. This finding gives urgency to defect control during epitaxial-growth and the design of appropriate field plate structures for the reliable high-voltage operation of MIS-HEMTs.