Benoit Gosselin

A Mixed-Signal Multichip Neural Recording Interface With Bandwidth Reduction

We present a multichip structure assembled with a medical-grade stainless-steel microelectrode array intended for neural recordings from multiple channels. The design features a mixed-signal integrated circuit (IC) that handles conditioning, digitization, and time-division multiplexing of neural signals, and a digital IC that provides control, bandwidth reduction, and data communications for telemetry toward a remote host. Bandwidth reduction is achieved through action potential detection and complete capture of waveforms by means of onchip data buffering. The adopted architecture uses high parallelism and low-power building blocks for safety and long-term implantability. Both ICs are fabricated in a CMOS 0.18-mum process and are subsequently mounted on the base of the microelectrode array. The chips are stacked according to a vertical integration approach for better compactness. The presented device integrates 16 channels, and is scalable to hundreds of recording channels. Its performance was validated on a testbench with synthetic neural signals. The proposed interface presents a power consumption of 138 muW per channel, a size of 2.30 mm2, and achieves a bandwidth reduction factor of up to 48 with typical recordings.

An Ultra Low-Power CMOS Automatic Action Potential Detector

We present a low-power complementary metal-oxide semiconductor (CMOS) analog integrated biopotential detector intended for neural recording in wireless multichannel implants. The proposed detector can achieve accurate automatic discrimination of action potential (APs) from the background activity by means of an energy-based preprocessor and a linear delay element. This strategy improves detected waveforms integrity and prompts for better performance in neural prostheses. The delay element is implemented with a low-power continuous-time filter using a ninth-order equiripple allpass transfer function. All circuit building blocks use subthreshold OTAs employing dedicated circuit techniques for achieving ultra low-power and high dynamic range. The proposed circuit function in the submicrowatt range as the implemented CMOS 0.18-mum chip dissipates 780 nW, and it features a size of 0.07 mm2. So it is suitable for massive integration in a multichannel device with modest overhead. The fabricated detector succeeds to automatically detect APs from underlying background activity. Testbench validation results obtained with synthetic neural waveforms are presented.

A Mixed-Signal Multi-Chip Neural Recording Interface with Bandwidth Reduction

We present the design of a multi-chip neural interface intended for multi-channel neural recording. The design features a mixed-signal part that handles neural signal conditioning, digitization and time-division multiplexing, and a digital part that provides control, bandwidth reduction, and serial communications towards a host interface. The two CMOS 0.18-mum fabricated embedded circuits that implement both parts are directly mounted on the back of a medical-grade stainless steel microelectrodes array and wire-bonded to its post-processed base. The presented neural interface integrates 16 channels for validation; however, the proposed approach is scalable to larger channel counts. In fact, it is suitable to implement microsystems including several hundreds of recording channels. The performance of the implemented multi-channel interface was validated with real neural waveforms.

Low-power implantable microsystem intended to multichannel cortical recording

We present in this paper an implantable massively parallel cortical data acquisition system. The proposed embedded mixed-signal (analog/digital) processing units are intended to be integrated on one chip, which will be flipped and connected on the top of a microelectrode array. Each channel is composed of a Chopper stabilized (CHS) low-power front-end to remove the 1/f noise, and a mixed-signal compression module using an analog wavelet transform (WT) processor that covers the entire neural signals bandwidth. The proposed front-end is based on a new rail-to-rail preamplifier topology and its circuit simulation under 0.18 /spl mu/m CMOS process demonstrates a power dissipation less than 25 /spl mu/W per channel. The main application of this medical device is to record action potentials evoked by visual stimuli, but it can be useful for several other cortical recording purposes.

An Ultra-Low-Power Successive-Approximation-Based ADC for Implantable Sensing Devices

Small area and power efficient analog-to-digital converters are needed to accommodate implantable multichannel sensors. This paper concerns the design and implementation of an ultra-low-power 8-bit successive approximation analog-to-digital converter (ADC). A new topology is proposed which improves the conventional architectures by replacing the successive approximation register and the digital-to-analog converter by a switchedopamp switched-capacitor circuit which dissipates very low power. The sampling frequency of the proposed ADC is 30 kSps and within an input range of 600 mV. Implemented in a 0.18-¿m CMOS process with a 1.8 V voltage supply, the ADC achieves a power dissipation of 7.4 ¿W and occupies an area of 0.04 mm2.

An ultra low-power chopper stabilized front-end for multichannel cortical signals recording

The design of an ultra low-power CMOS chopper stabilized front-end suitable for a fully implantable cortical data acquisition system (CDAS) is presented The proposed low-power front-end improves recording quality and is area efficient. It removes low frequency noise and achieves submicrovolt input offset. The key to its performances is chopper modulation technique, usage of weakly inverted transistors and a supply voltage of 0.9 V. The chopper amplifier is composed of a low-noise preamplifier combined with a 2/sup nd/ order micropower bandpass Gm-C filter. The preamplifier achieves an input referred noise of less than 30 nV//spl radic/Hz. A whole channel dissipates less than 20 /spl mu/W and has been implemented in 0.18 /spl mu/m CMOS.

Adaptive detection of action potentials using ultra low-power CMOS circuits

We present ultra low-power CMOS analog circuits for automatic detection of action potentials (APs). The proposed detection strategy locates AP waveforms and completely preserves their integrity. An adaptive threshold is implemented using a local time-averaging filter presenting a large time constant. The filter uses very small transconductances implemented by means of dedicated circuit techniques and subthreshold operation of MOS transistors. Also, a compact voltage squarer pre-processor is introduced to emphasize neural APs prior to detection. The proposed circuits were implemented in a CMOS 0.18-mum process and achieve ultra low-power consumption. Both circuits have been validated in simulations with synthetic neural waveforms. The adaptive threshold circuit dissipates only 27.2 nW, whereas the voltage squarer dissipates 76.7 nW.

A low-power bioamplifier with a new active DC rejection scheme

We present a bioamplifier suitable for massive integration in implantable recording medical devices. This amplifier achieves reduced size and lower power consumption, compared to previous designs, by means of a novel DC rejection scheme. DC rejection is achieved by an active integrator located in the feedback loop of the bioamplifier. It places a highpass cutoff frequency within the transfer function, which is set by a small capacitor and a MOS-Bipolar equivalent resistor. This configuration rejects large DC offset and drift that exist at the electrode-electrolyte interface without the need for input RC networks or area consuming capacitors feedback networks, thus preserving the bioamplifiers high input impedance and small size. The proposed bioamplifier, designed in a 0.18-mum CMOS process, provides a midband gain of 53 dB, passes the neural signal from 105 Hz to 9.2 kHz and achieves an input-referred noise of 5 muVrms. It occupies less than 0.064 mm2 and dissipates 8.4muW

Circuits techniques and microsystems assembly for intracortical multichannel ENG recording

We present dedicated circuit techniques and strategies to design and assemble dense multi-channel microsystems intended for ENG recording. Efficient neural interfacing circuits are proposed and high-fidelity data reduction strategies are demonstrated. Also, an on-chip power management scheme based on automatic biopotential detection is suggested. The presented strategy is expected to improve power consumption in multi-channel ENG sensors by an order of magnitude. Low-power design techniques, ultra-low-power neural signal processing circuits, and dedicated implementation strategies to achieve high integration density in multi-channel microsystems are also covered.

An ultra low-power CMOS action potential detector

We present a low-power CMOS analog circuit for automatic detection of action potentials (APs) in extracellular recordings. The detector emphasizes neural APs by means of an energy-based preprocessor and locates them with a precision comparator. A linear-phase delay filter allows signal buffering to avoid truncated waveforms. The proposed detector isolates the identified waveforms in their entirety and completely preserves their features in order to improve shapes discrimination. The proposed circuit, implemented in a CMOS 0.18-mum process, achieves ultra low-power consumption as the whole detector dissipates only 781.5 nW. The detector has been validated in simulations with real neural signals and successfully detects APs from the underlying background activity.