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Featured researches published by Bernard J. New.


custom integrated circuits conference | 2006

Die Stacking Technology for Terabit Chip-to-Chip Communications

Arifur Rahman; John Trezza; Bernard J. New; Stephen M. Trimberger

In this paper a die stacking technology, leveraging on through die via (TDV) integration and wafer bonding, is presented. Using state-of-the-art volume manufacturing environment, 10:1 aspect ratio TDV and wafer-level bonding technology are developed and initial electrical and reliability characterization results of TDVs are provided. The opportunities for die-stacking technology to alleviate chip-to-chip communication bottleneck are discussed and visions for stacked-die applications, utilizing a programmable virtual backplane, are presented


Archive | 1993

Logic structure and circuit for fast carry

Bernard J. New


Archive | 1997

Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM

Bernard J. New; Robert Anders Johnson; Ralph D. Wittig; Sundararajarao Mohan


Archive | 1997

Field programmable gate array with dedicated computer bus interface and method for configuring both

Bernard J. New


Archive | 2001

Configurable logic element with expander structures

Bernard J. New; Ralph D. Wittig; Sundararajarao Mohan


Archive | 2003

Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice

Bernard J. New


Archive | 2001

Method and apparatus for incorporating a multiplier into an fpga

Bernard J. New; Steven P. Young


Archive | 1997

Field programmable gate array with distributed gate-array functionality

Bernard J. New


Archive | 2000

Dedicated function fabric for use in field programmable gate arrays

Bernard J. New


Archive | 2004

Programmable logic device with cascading DSP slices

James M. Simkins; Steven P. Young; Jennifer Wong; Bernard J. New; Alvin Y. Ching

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