Bernd Roelfs

Filling through holes and blind microvias with copper using reverse pulse plating and insoluble anodes

Purpose – The purpose of this paper is to present a summary of development work made in technical centres and on the subsequent customer qualification of copper filled through holes and blind microvias.Design/methodology/approach – Various copper deposition parameters were investigated in a small‐scale production line which was then extended to full‐scale production qualification in a horizontal conveyorised system. Samples of substrates with copper filled through holes were qualified at end‐user facilities.Findings – The copper plating process may be used to replace an existing production process for printed circuit boards. The proposed system can give a more reliable result in terms of filling and technical capability for the produced substrate. Overall production cost savings are possible.Research limitations/implications – The technology is based on a copper plating electrolyte using a redox pair for copper replenishment. The results achieved depend on use of this system and on production equipment wh...

Electrolytic solder deposit for next generation flip chip solder bumping

Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate solder paste. The continuing trend towards increasing miniaturisation and the associated decrease in size of solder resist opening, SRO is causing production difficulties with the stencil printing process. Practical experience of production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 0.15 mm for these applications.

Simultaneous front and back side Cu metallization on power chips

This article describes a new tool and process for Cu electroplating on power chips. The tool enables a new, more efficient method for embedding power chips by means of simultaneous electroplating on both sides of the wafer. Additional tool features, to be discussed in this article, provide technical benefits for embedded technologies and enable further miniaturization of power chip packages to comply with future requirements and products.

MultiPlate- from wafer to panel-new solutions for electrolytic cu deposition in advanced packaging

Next generation technologies require an adaptation of the advanced packaging industry. Our industry has to answer the question of how to meet these new challenges such as i) plating copper (Cu) redistribution layers (RDL) of less than 5μm line and space (L/S) in volumes without significant yield losses and ii) plating Cu pillars with much higher speed than current systems. This will require new technology solutions. Currently, there are mainly two different strategies in the industry to cope with these challenges: a) Fan Out Wafer Level Packaging (FOWLP) solutions, such as TSMCs Integrated Fan Out Technology (InFO) and Amkors Silicon Wafer Integrated Fan Out Technology (SWIFT) packages and b) Panel level solutions using new materials like glass, or new embedding processes are also coming to the market.

Electroless deposition of Nickel-Palladium-Gold for high reliability and power application: Cost and performance progress

Electroless deposited metal stacks of Nickel-Palladium-Gold (ENEPIG) or Nickel-Palladium (ENEP) are frequently used in modern advanced packaging technologies. Main application for this metal stack is the under bump or pad metallization (fig1.). The surface of this specific metal stack allows for reliable wire bonding including thick Copper wire bonding as well as for soldering on the die. This technology has been successfully adopted by automobile suppliers as well as power chip manufacturers. Recently it has been introduced for housing redistribution layers of Copper (see fig. 2). In this paper we are presenting the latest improvements over the entire ENEP(IG) process leading to a substantial Cost of Ownership (CoO) reduction. Improvements span chemistry control, manufacturing process, the plating process itself and tool layout. We are discussing how this has been achieved and how strong this is influencing the cost for the overall process steps. Different tool concepts for the ENEPIG process will be discussed, with a focus on benefits of specific spray pre-treatment as this is a key enabler for fine line applications.

Electrolytic solder deposit for next generation flip chip solder bumping: 2010 International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT) conference

Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate solder paste. The continuing trend towards increasing miniaturisation and the associated decrease in size of solder resist opening, SRO is causing production difficulties in particular associated with achieving sufficient yields with the stencil printing process. Practical experience of current production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 0.15 mm for these applications. Also the increased costs associated with low yields are an ever present factor. This paper describes a novel approach to replace the stencil printing process by use of an electrolytic deposition of solder. In contrast to stencil printing, use of electrolytic deposition techniques allows production of solder bumps with a pitch below 0.15 mm and with a SRO below 80 jim. The electrolytic deposition of tin requires an electrical connection to each surface for metal deposition; this process is shown as made using an appropriate copper seed layer which is produced onto the structured soldermask. Specially modified activation and electroless copper processes are introduced for this critical process step. Following this the use of a photo sensitive plating resist defines the SRO which is then filled with the electrolytic tin deposit. The associated processes required both for seed layer production and for removal of plating resist and subsequent etching of the seed layer are described and first qualification results are shown from the complete process. Methods for production of electrolytic solder bumps based on pure tin as well as alloys of tin/copper are shown and in particular a method to control the alloy concentration of electroplated tin/copper bumps. Test results with both alloy system and also pure tin bumping are presented together with comparison of the advantages and disadvantages. This newly developed Sn/Cu plating process allows for a simultaneous plating of both sides of IC Substrates, the C4 and the BGA side of the panel. On the C4 side the complete Sn/Cu solder ball is plated whereas on the BGA side the basis for the subsequent placement of a larger solder ball can be achieved. Examples are given for such a process flow using the photo resist process on top of a solder resist. As a further development of the solder bumping process the photo resist free sequence is introduced which uses a modified tin deposition electrolyte to produce tin filled structures directly onto the structured and prepared soldermask. This process offers optimum solder bump plated distribution and the potential for further cost savings due to the elimination of critical processing steps associated with photo imaging.

From thin cores to outer layers: Filling through holes and blind micro vias with copper by reverse pulse plating

This paper presents new advancements in copper electroplating technology for both Blind Micro Vias and Through Holes. Processes and manufacturing technology are described as well as current limitations and requirements. As a highlight the complete filling of through holes with electroplated copper by Reversed Pulse Plating, RPP, is described. Both Blind Micro Via and Through Hole filling using this technology are already targeted for production at HDI and also at the packaging level. The basis of the latest advancements has been the development of the so called SuperFilling™ process. SuperFilling™ combines the electrolytic reverse pulse deposition of copper into specific structures together with the simultaneous etching of copper from the substrate bulk surface in a continuous panel plating step. This combination reduces the amount of overplated Cu by up to 50% compared to conventional copper deposition processes for HDI fine line applications. The SuperFilling™ mechanism as well as manufacturing requirements and production supervision tools such as online analysis are described in detail. The latest development, through hole filling by RPP, offers a viable alternative to the standard paste plugging for core processing in substrate manufacturing. Current core manufacturing requires a paste plugging process for through holes so that subsequent build up layers can be produced by sequential lamination, the flat core surface is essential for stacked via and also via in pad technology. This paste plugging process requires additional process steps, each of which has its own limitations and contributes to the overall cost. Filling the core through vias by electroplating can eliminate the plugging process and significantly reduces the number of overall process steps which will also reduce costs. Moreover, it offers certain advantages such as potentially higher reliability in accelerated aging tests and an improved thermal management as the thermal conductivity of a completely copper filled through via is significantly higher than a paste plugged through via. First manufacturing experiences with the Through Hole filling technology are presented along with a discussion of its manufacturing prerequisites and limitations.