Bernhard Goll

A Comparator With Reduced Delay Time in 65-nm CMOS for Supply Voltages Down to 0.65 V

A comparator in a low-power 65-nm complementary metal-oxide-semiconductor process (only standard transistors with threshold voltage Vt ap 0.4 V were used) is presented, where the circuit of a conventional latch-type comparator consisting of two cross-coupled inverters is modified for fast operation, even with 0.6 GHz at a low supply voltage of 0.65 V. The advantages of a high-impedance input, rail-to-rail output swing, robustness against the influence of mismatch, and no static power consumption are kept. To achieve a bit error rate of 10-9 at 1.2-V supply, an amplitude at the input of 16.5 mV at 4 GHz has to be applied. If the supply voltage is lowered, 12.1 mV at 0.6 GHz/0.65 V is necessary. The power consumption of the comparator is 2.88 mW at 5 GHz (1.2 V) and 128 muW at 0.6 GHz (0.65 V). Simulations show an offset standard deviation of about 6.1 mV at 0.65-V supply. With an on-chip measurement circuit, the delay time of the comparator of, e.g., 104 ps for 15-mV input amplitude at 1.2-V supply, is obtained.

A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47µW at 0.6V

Clocked regenerative comparators, which use positive feedback of a latch to force a fast decision, are used for many applications. In [1] a 10GHz 3-stage comparator in 1.2V 0.11µm CMOS is presented and is designed to extract every 4th bit of a 40Gb/s data stream. A BER≪10−12 for 1Vpp at the input is achieved. Depending of the intended application, the constant tail current and the low-voltage swing of the CML blocks may or may not be beneficial. In [2] a latch-type sense amplifier (in 1.5V 0.13µm CMOS) for use in SRAMs is investigated. The delay time is 119ps for an input voltage difference of 100mV. A disadvantage is that for proper operation a sufficiently large supply voltage is needed due to the stack of transistors and therefore the comparison time is longer than 11ns at 0.7V. In [3] a comparator with similar circuit structure in 1.8V 0.18µm CMOS is described, consuming 350µW at 1.4GHz. The standard deviation of the offset without compensation is σ=31.6mV. The sense-amplifier presented in [4] (1.2V 90nm CMOS, 225µW @ 2GHz) also consists of a typical latch with two cross-coupled CMOS inverters. The comparator in [5] (1.5V 0.12µm CMOS, low-threshold transistors) reaches a sensitivity (BER=10−9) of 16.5mV @ 4GHz/1.5V and 25.8mV @ 500MHz/0.5V. The design of the latch still needs static current and so 2.65mW is needed at 6GHz/1.5V.

Nonlinear Current Control for Power Electronic Converters: IC Design Aspects and Implementation

This letter provides design guidelines and presents a fully integrated implementation of the recently proposed nonlinear average current control (NACC) algorithm for power factor correction and dc–dc converters. The control performance and dynamics of the current-mode controlled power electronic converter strongly depends on the accuracy of the applied current sensing method. Several current sensing methods have been proposed in the literature, including the senseFET method, which is suitable for on-chip current measurement. This letter presents a modification of the senseFET on-chip current sensing technique dedicated for an ultrahigh sensing ratio and suited for the current sensing processing, which gives current-type output what fits well with the NACC control method, thus further simplifying the converter design and reducing cost as well as noise sensitivity of the control circuitry. Hence, the need for a voltage-to-current and current-to-voltage transformation circuit is eliminated. Therefore, the proposed method of the current sensing is applicable to any boost-like converter, whose control system requires an extremely high sensing ratio to be achieved. Nevertheless, it is especially well suited to be combined with an NACC control circuitry irrespective of the required sensing ratio. Experimental results verify the proposed design done in 0.35-μm HV triple-well CMOS technology.

A 0.12μm CMOS Comparator Requiring 0.5V at 600MHz and 1.5V at 6GHz

This comparator has 2 active-load PMOS transistors that can be used to reset the output nodes to the supply level. An NMOS transistor added in the clock line controls the active loads to avoid additional reset switches and continuously biased load transistors. Two NMOSTs added in the input differential amplifier reduce the power consumption, which is 18μW at 0.5V and 600MHz, and 2.65mW at 1.5V and 6GHz

A clocked, regenerative comparator in 0.12μm CMOS with tunable sensitivity

This paper presents a clocked, regenerative comparator in a 1.5V/0.1mum CMOS technology, where the sensitivity is tuned by separately adjusting the tail currents of the latch and the input amplifier. The comparator reaches a sensitivity of 3.9mV (2GHz) and 9.2mV (3GHz) to achieve a Bit Error Rate (BER) of 10-9 . The power consumption of the comparator is 422muW at 2GHz and 584muW at 3GHz. The simulated standard deviation of the offset is sigma=16.1mV. Finally a circuit extension is proposed, where only with an additional resistor the influence of noise and mismatch can be reduced.

A Low-Power 4GHz Comparator in 120nm CMOS Technology with a Technique to tune Resolution

This paper presents a comparator with the capability of a high decision speed, but static power consumption was avoided. Furthermore the circuit implements a technique to enhance resolution while keeping the ability of a high switching speed. During the reset phase the comparator is pulled to ground level, which defines a logic voltage level. A test chip with the comparator was manufactured in a 120nm CMOS technology with a supply-voltage of 1.5V. For a bit-error-rate (BER) of 10-9 the presented comparator is able to detect 11.2mV at 2GHz, 20mV at 3GHz, 26mV at 3.5GHz and 118mV at 4GHz. The power consumption was 788muW at 3.5GHz and 812muW at 4GHz

A low-power 2-GSample/s comparator in 120 nm CMOS technology

This paper presents a comparator in 120nm digital CMOS technology with a supply voltage of 1.5V. In contrast to common comparator structures a delayed reset signal is used to enhance the output voltage difference with the help of charge injection. Furthermore the body effect of p-MOS transistors with their separated n-wells are used to lower their threshold voltage to have an increase in resolution. For characterization several BER (bit-error-rate) measurements on the comparator have been made. For a BER of 109 the comparator is able to detect an input voltage difference of 9.5mV at a clock frequency of 1.5GHz and 16mV at 2.0GHz. The maximum power consumption of the comparator with two following additional transfer stages is 360/spl mu/W at 2.0GHz.

A DC-to-8.5 GHz 32 : 1 Analog Multiplexer for On-Chip Continuous-Time Probing of Single-Event Transients in a 65-nm CMOS

A multiplexer circuit that is capable of accessing 32 internal nodes for the continuous-time probing of signal waveforms is proposed. A chip has been fabricated with eight multiplexer instances and used in experiments for monitoring radiation-induced single-event transients in digital circuits. Pulses with a width of less than 100 ps and pulses over 1 V in height were observed for 230-MeV particle hits. Measurements show 8.5 GHz, −3-dB bandwidth, and a 1.92% total harmonic distortion for a 1-V input range, and a 6.58% total harmonic distortion for a 2-V input range. The measured dynamic range is nominally 26.5 dB.

Synchronous OEIC integrating receiver for optically reconfigurable gate arrays

A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35 μm opto-CMOS process fed at 3.3 V and due to the highly effective integrated pin photodiode it operates at μW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of −26.0 dBm and −25.5 dBm are achieved, respectively, for λ = 635 nm and λ = 675 nm (BER = 10−9 ) with an energy efficiency of 2 pJ/bit.

10 Gb/s Switchable Binary/PAM-4 Receiver and Ring Modulator Driver for 3-D Optoelectronic Integration

This paper presents ring modulator driver and receiver circuits designed for three-dimensional photonic-electronic integration using interwafer connections, whose parasitic capacitance is expected to be in the order of 15 fF. Both transmitter and receiver can operate with binary and PAM-4 modulation at 10 Gb/s. To the authors knowledge, it is the first PAM-4 ring modulator driver being presented. The circuits are designed in AMS 0.35-μm SiGe BiCMOS technology with total power consumptions of 160 and 180 mW for transmitter and receiver, respectively. The receivers sensitivity is -27 dBm for binary and -22 dBm for 4-PAM signals both at a photodiode responsivity of R = 0.9 A/W. A monitor transimpedance amplifier with sensitivity -32 dBm was also designed in order to control the operating point of the ring modulator.