Bertrand Rousseau

An evaluation of dynamic partial reconfiguration for signal and image processing in professional electronics applications

Signal and image processing applications require a lot of computing resources. For low-volume applications like in professional electronics applications, FPGA are used in combination with DSP and GPP in order to reach the performances required by the product roadmaps. Nevertheless, FPGA designs are static, which raises a flexibility issue with new complex or software defined applications like software-defined radio (SDR). In this scope, dynamic partial reconfiguration (DPR) is used to bring a virtualization layer upon the static hardware of FPGA. During the last decade, DPR has been widely studied in academia. Nevertheless, there are very few real applications using it, and therefore, there is a lack of feedback providing relevant issues to address in order to improve its applicability. This paper evaluates the interest and limitations when using DPR in professional electronics applications and provides guidelines to improve its applicability. It makes a fair evaluation based on experiments made on a set of signal and image processing applications. It identifies the missing elements of the design flow to use DPR in professional electronics applications. Finally, it introduces a fast reconfiguration manager providing an 84-time improvement compared to the vendor solution.

NoC Implementation in FPGA using Torus Topology

With the increasing capacity of FPGAs following the Moores law, it is possible to build in a single FPGA, a large system on chip (SoC) composed by several cores. Their performances depend strongly on their interconnection structure. Traditional and hierarchical busses are not suitable to be used. The Networks on Chip (NoC), due to their characteristics such as scalability, flexibility, high bandwidth, have been proposed as a valid approach to meet communication requirements in SoC. Most of the current NoCs uses mesh topology. With mesh topology/, central channels are significantly solicited. This often leads to the congestion of the center area of the mesh. The solution for such situation is to add routers in the mesh or to use torus topology which, with the symmetry introduced on the routers in the opposite edges, has a good behavior to face congestion, and this, with a small increase of resources. In this paper, we propose a scalable implementation of a NoC for FPGA using torus topology. We proposed router architecture, a routing algorithm and a solution to the problem introduced by the long wires in torus topology.

Enabling certification for dynamic partial reconfiguration using a minimal flow

As the trend in reconfigurable electronics goes towards strong integration, FPGA devices are becoming more and more interesting. They are already used for safety-critical applications such as avionics (Hispano-Suiza, 2005). Latest FPGAs also enable new techniques such as dynamic partial reconfiguration (DPR), allowing new possibilities in terms of performance and flexibility. Their use in safety-critical systems is considered as impossible nowadays since they must be strictly validated, and DPR brings many new issues. Indeed, the tools used for DPR must be certified, which is barely impossible for the current DPR tools provided by the vendors. We have developed a simple flow upon the usual static one for Xilinx FPGAs that does not require any support of the vendor tools for DPR. This lessens the complexity of tools certification, and make a step towards enabling the certification of DPR for safety-critical applications. Moreover, under strong hypotheses, and by using safe design principles, we show how the complexity of certifying DPR can be reduced

Dynamically reconfigurable architectures for software-defined radio in professional electronic applications

Professional embedded electronic applications are found in military, security, or high reliability systems like in avionics and aerospace. They have to meet specific requirements, and they are produced in low or even very low volumes. In this field of applications, telecommunication applications have to face a diversity issue due to the high number of dedicated standards, that are far more numerous than in consumer electronics. Software-defined radio is a very promising technology to solve this issue. Nevertheless, it is a very challenging application that requires high flexibility and high performances. FPGAs are interesting solutions for professional electronic applications thanks to their reconfigurability and their high computation capability. An emerging technique, called dynamic partial reconfiguration allows to bring even more flexibility to FPGAs. This chapter presents the advantages and impacts of leveraging dynamic partial reconfiguration in regards to the requirements of professional electronics and software-defined radio.

A methodology for precise comparisons of processor core architectures for homogeneous many-core DSP platforms

The power efficiency of an HMCP heavily depends on the architecture of its processor cores. It is thus very important to choose it carefully. When comparing processing architectures for their use in a many-core platform, one must evaluate its IPC, but also its power and area. Precise power and area evaluations can only be done with real implementations. However, comparing processor implementations is a difficult task since the implementation specifities introduce interferences on the performances. This paper proposes a methodology that allows to realize precise comparisons of performance for different processor architectures. Using this methodology, it is possible to choose the best architecture for an HMCP targeting DSP applications. The methodology is based on the use of a common architural template to build the cores, and on the application of specific optimizations when relevant. In order to validate the methodology, three RISC cores are implemented: a single-issue core, and two VLIW processors with respectively 3 and 5 issues. The implemented cores are precisely compared on a set of DSP kernels.