Bhanu Kapoor

Improving the Accuracy of Circuit Activity Measurement

A novel measure of activity in digital circuits, called transition density, along with an efficientalgorithm to compute the density at every circuit node, has been proposed in [1]. However, the efficiency of this algorithm is achieved at the cost of accuracy in the density values. This leaves much to be desired for its use in applications which require more accurate activity measurements at each node in the circuit e.g., circuit optimization problems with a low power goal. The complexity of this problem lies in computing the Boolean difference probabilities at each node of the circuit. In this paper, an efficientalgorithm for computing these probabilities is described. This allows the activity measurements, within a circuit partition, to be carried out in a more efficientmanner compared to the well known approach of computing these probabilities. Larger circuit partitions, where each node within a partition is solved accurately with respect to that partition, result in more accurate activity measurements. An efficientcircuit partitioning algorithm, with the goal of maximizing the number of correlated nodes within each partition, has been developed. This allows more accurate measurements compared to a randomly selected set of partitions. These methods have been incorporated in an improved simulator for circuit activity measurement. Some results obtained on the ISCAS85 benchmark circuits are included.

Low power storage exploration for H.263 video decoder

We describe a power exploration methodology for data-dominated applications using a H.263 video decoding demonstrator application. The starting point for our exploration is a C specification of the video decoder, available in the public domain from Telenor Research. We have transformed the data transfer scheme in the specification and have optimized the distributed memory organization. This results in a memory architecture with significantly reduced power consumption. For the worst-case mode using predicted and bi-directional (PB) frames, memory power consumption is reduced by a factor of 9. To achieve these results, we make use of our formalized high-level memory management methodology, partly supported in our ATOMIUM environment.

Low-power data transfer and storage exploration for H.263 video decoder system

We describe a power exploration methodology for data-dominated applications using a H.263 video decoding demonstrator application. The starting point for our exploration is a C specification of the video decoder, available in the public domain from Telenor Research. We have transformed the data-transfer scheme in the specification, and have optimized the distributed memory organization. This results in a memory architecture with significantly reduced power consumption. For the worst case mode using predicted (P) frames, memory power consumption is reduced by a factor of 7 when compared to the reference design. For the worst case mode using predicted and bi-directional (PB) frames, memory power consumption is reduced by a factor of 9. To achieve these results, we make use of our formalized high-level memory management methodology, partly supported in our ATOMIUM environment.

An efficient method for computing exact path delay fault coverage

We describe algorithms and data structures for accurate and efficient computation of path delay fault coverage. Our method uses an interval-based representation of consecutively numbered path delay faults. We describe a modified 2-3 tree data structure to store and manipulate these intervals to keep track of tested faults. Some results obtained using non-robust simulation of benchmark circuits suggest the viability of this approach.<<ETX>>

Low power memory architectures for video applications

We provide data and insight into how the choice of cache parameters affects memory power consumption of video algorithms. We make use of memory traces generated as a result of running typical MPEG-2 motion estimation algorithms to simulate a large number of cache configurations. The cache simulation data is then combined with on-chip and off-chip memory power models to compute memory power consumption. In the area of analysis of video algorithms, this paper focuses on the following issues: we provide a detailed study of how varying cache size, block size, and associativity affects memory power consumption. The configurations of particular interest are the ones that optimize power under certain constraints. We also study the role of process technology in these experiments. In particular, we look at how moving to a more advanced process technology for the on-chip cache affects optimal points of operation with respect to memory power consumption.

Improved technology mapping using a new approach to Boolean matching

We present an improved method for technology mapping using a new approach to the Boolean matching problem. Signatures computed over OBDDs using a set of specific probability values determine matches between library cells and portions of the netlist. Unlike some previous methods, which may require creation of up to O(n!) OBDDs for all possible permutations of modules inputs, our method requires exactly one OBDD to be created for the portion of the netlist being matched. Some results obtained on ISCAS85 benchmark circuits suggest the viability and validity of our approach.<<ETX>>

Analyzing memory bandwidth requirements of video algorithms

Memory bandwidth is emerging as the fundamental impediment to higher performance and lower power computer and communication systems. In this paper, we present an analysis of memory bandwidth requirements for the H.263 video codec algorithms. We make use of memory traces generated as a result of running Telenors H.263 video encoder and decoder software implementations to simulate a large number of cache configurations. In the area of analysis of video algorithms, this paper focuses on the following issues: We provide a study of how varying cache size, block size, associativity, replacement policy, and organization parameters such as split versus unified cache affects memory bandwidth requirements. A comparative study of encoder and decoder bandwidth requirements is presented. We also study various advanced encoding options provided with the H.263 standard in this light. Based on our study, we provide guidelines for traffic-directed memory system design.

Computing exact path delay-fault coverage using OBDDs

Symbolic representation of path delay-faults can achieve high degree of compaction relative to more explicit forms. Large numbers of path delay-faults exist in common digital circuits. Ordered binary decision diagrams (OBDDs) provide a convenient data structure to represent these large number of path delay faults during the process of fault simulation computing the path delay-fault coverage for a given delay test-set. We present some experimental results from applying these algorithms to common benchmark examples that demonstrate the viability of our approach.

An efficient tree-based algorithm for computing path delay fault coverage

A new algorithm for the efficient computation of path delay fault coverage for circuits with very large number of path delay faults has been presented. The directed acyclic graph representing a combinational circuit consists of a set of trees rooted at the fanout and output nodes. The algorithm uses a tree-based marking process to compute the path delay fault coverage of a given delay-test set in linear time and memory. The root of a tree is marked as used only when it has been tested with respect to the rising and falling path delay faults passing through all the leaves of the tree. The algorithm takes advantage of large tree structures found in most digital designs, to provide a reasonably accurate and very efficient method for the estimation of path delay fault coverage. Some results obtained using non-robust simulation of benchmark circuits suggest the viability and validity of our approach.<<ETX>>

Analysis of memory bandwidth requirements for the H.263 video codec

Memory bandwidth is emerging as the fundamental impediment to higher performance and lower power computer and communication systems. In this paper, we present an analysis of memory bandwidth requirements for the H.263 video codec algorithms. We provide data and insight into how the choice of cache parameters affects external bandwidth requirements of video. We make use of memory traces generated as a result of running Telenors H.263 video encoder and decoder software implementations to simulate a large number of cache configurations. In the area of analysis of video algorithms, this paper focuses on the following issues: we provide a study of how varying cache size, block size, associativity, replacement policy, and organization parameters such a split versus unified cache affects memory bandwidth requirements. A comparative study of encoder and decoder bandwidth requirements is presented. We also study various advanced encoding options provided with the H.263 standard in this light. Based on our study, we provide guidelines for traffic-directed memory system design.