Patrick W. Bosshart

A System for Incremental Synthesis to Gate-Level and Reoptimization Following RTL Design Changes

We address the problem of long cycle time associated with the basic method of optimizing VLSI circuits. We are developing a system which makes it possible to carry out arbitrary changes to Register Transfer Level (RTL) source description of the circuit after a gate-level implementation has been synthesized. The system incrementally updates the gate-level implementation. For typical changes this updation produces comparable results but requires only a small fraction of the time for a complete resynthesis. The system makes use of two object representations. We describe these representations, the maintenance of consistency between them and the incremental synthesis and reoptimization process. Status of the ongoing research on this system is presented.

Circuit optimization techniques in DROID

Circuit-level optimization techniques such as buffer insertion, gate input reordering and transistor sizing are commonly practiced by circuit designers to deliver high performance circuits. All these techniques are indispensable in shortening the design cycle and in improving the delay performance. The authors describe the algorithms implementing these circuit optimization techniques which allow push-button, high-performance synthesis within the DROID Auto-Full-Custom design system.<<ETX>>

Cache parameters and memory power consumption of video algorithms

Energy efficient computing is growing in demand as portable systems require energy efficiency in order to maximize the battery life. Memory power consumption is becoming an increasingly larger fraction of the total power consumption of a given system. In this paper, we provide data and insight into how the choice of cache parameters affects memory power consumption of video algorithms. We make use of memory traces generated as a result of running typical MPEG- 2 motion estimation algorithms to simulate a large number of cache configurations. The cache simulation data is then combined with on-chip and off-chip memory power models to compute memory power consumption. We provide a detailed study of how varying cache size, block size, and associativity affects memory power consumption. The configurations of particular interest are the ones that optimize power under certain constraints. We also study the role of process technology in these experiments. In particular, we look at how moving to a more advanced process technology for the on-chip cache affects optimal points of operation with respect to memory power consumption.

A linear time algorithm for timing directed circuit optimizations

This paper describes an algorithm for doing timing directed circuit optimizations in linear time. An optimal gate input reordering scheme for performance improvement, and a gate sizing scheme for both performance improvement and area reduction is presented. The algorithm uses a combination and extent of partial validity of timing delays in obtaining linear runtime performance. The algorithm has been applied for gate input reordering and BiCMOS deselection in designs targeted for a BiCMOS gate array. At an average in linear time, a 50% reduction in BiCMOS site utilization, and a 5% gain in design performance through reordering has been achieved.<<ETX>>