Bharat Deep Rathi

Speed up of test generation using high-level primitives

We propose a general methodology to speed up the test generation process for circuits with high-level primitives. Our search procedure is a variation of depth first search that tries to fully exploit the capabilities of a computer to execute complex arithmetic and logical operations. We present techniques for signal value justification, and fault propagation, which are used by our algorithm. We have implemented a dependency-directed backtracking method to speed up our algorithm. This methodology has been applied to six circuits and the results are found to be very encouraging.

An evaluation of the memory reference behavior of engineering/scientific applications in parallel systems

This paper presents the results of a study conducted to evaluate the inherent memory reference behavior of several engineering/scientific applications, executing on shared memory, MIN-based, parallel systems. In this study, system sizes of two to 64 processors were evaluated. A trace-driven simulation model was used to obtain dynamic reference characteristics of the code. Included in this code were explicit declarations of shared variables. Our results indicate that a significant amount of explicitly declared shared data is accessed as either readonly by several processors, or read-write by a single processor. Furthermore, lines containing synchronization variables tend to see small ownership times at a processor and are accessed by several processors in the system. We also note that, as expected, relatively more references are to data with smaller ownership times, as the number of processors increase. Finally, the application data set size can have an impact on ownership time, as the number of processors increase.

A functional diagnostics methodology

The functional diagnostic methodology (FDM) used to develop the diagnostics for the research parallel processor prototype (RP3) is described. The FDM approach uses the instruction set to diagnose the computer system. In order to optimize the size of the diagnostic procedures, the subsystem is partitioned into modules, and the modules are further divided into a set of submodules or primitive logic components. The diagnostic procedures to test these basic submodules procedures to test these basic submodules and primitive logic components are then developed. The fault model that describes the failure modes considered in the FDM is presented. The FDM is illustrated using the ROMP processor as an example.<<ETX>>