Bharat Joshi

Fault-Tolerant Computing

This chapter provides an overview of fault-tolerant computing. Fault-tolerant computing can be defined as the process by which a computing system continues to perform its specified tasks correctly in the presence of faults with the goal of improving the dependability of the system. Principles of fault-tolerant computing as well as various fault-tolerant architectures are discussed. The article concludes by observing trends in the fault-tolerant computing. Keywords: fault tolerance; reliability; availability; coverage; dependability; redundancy

Efficient parallel testing and diagnosis of digital microfluidic biochips

Microfluidics-based biochips consist of microfluidic arrays on rigid substrates through which movement of fluids is tightly controlled to facilitate biological reactions. Biochips are soon expected to revolutionize biosensing, clinical diagnostics, environmental monitoring, and drug discovery. Critical to the deployment of the biochips in such diverse areas is the dependability of these systems. Thus robust testing and diagnosis techniques are required to ensure adequate level of system dependability. Due to the underlying mixed technology and mixed energy domains, such biochips exhibit unique failure mechanisms and defects. In this article efficient parallel testing and diagnosis algorithms are presented that can detect and locate single as well as multiple faults in a microfluidic array without flooding the array, a problem that has hampered realistic implementation of several existing strategies. The fault diagnosis algorithms are well suited for built-in self-test that could drastically reduce the operating cost of microfluidic biochip. Also, the proposed alogirthms can be used both for testing and fault diagnosis during field operation as well as increasing yield during the manufacturing phase of the biochip. Furthermore, these algorithms can be applied to both online and offline testing and diagnosis. Analytical results suggest that these strategies that can be used to design highly dependable biochip systems.

Performance analysis of coarse-grained parallel genetic algorithms on the multi-core sun UltraSPARC T1

The new generation of shared memory multi-core processors with multiple parallel execution paths provides a promising hardware platform for applications with high degree of task-level parallelism (TLP). Genetic Algorithm (GA), a widely-used evolutionary meta-heuristic optimization method, is a unique candidate in this class of applications and demonstrates significant amount of explicit and implicit parallelism. In this paper, we present the performance characteristics of a GA optimizing a placement problem on a Sun UltraSPARC T1 processor. To investigate the behavior of the benchmark, we vary both algorithm-specific parameters as well as the size of the target problem. The system performance is evaluated by monitoring throughput, cycle-per-instruction (CPI) and, the memory access patterns for different core and thread combinations. Our experiments show that for a constant data size, as the number of threads per core increase from 1 to 4, the throughput of the system increases by 84% keeping all cores active. Similarly, as we increase the number of cores in the system, the throughput of the system increases by a factor of 3. The average memory bandwidth is seen to scale in proportion to throughput for both core-scaling and thread-scaling. The overall increase in throughput, either by core-scaling or thread-scaling, in spite of growing memory bandwidth, shows the ability of the multi-threaded multi-core processor to hide long latency memory accesses for the targeted benchmark.

Multiple fault diagnosis in digital microfluidic biochips

Microfluidics-based biochips consist of microfluidic arrays on rigid substrates through which, movement of fluids is tightly controlled to facilitate biological reactions. Biochips are soon expected to revolutionize biosensing, clinical diagnostics, and drug discovery. Critical to the deployment of biochips in such diverse areas is the dependability of these systems. Thus, robust testing techniques are required to ensure an adequate level of system dependability. Due to the underlying mixed technology and energy domains, such biochips exhibit unique failure mechanisms and defects. In this article we present a highly effective fault diagnosis strategy that uses a single source and sink to detect and locate multiple faults in a microfluidic array, without flooding the array, a problem that has hampered realistic implementations of all existing strategies. The strategy renders itself well for a built-in self-test that could drastically reduce the operating cost of microfluidic biochips. It can be used during both the manufacturing phase of the biochip, as well as field operation. Furthermore, the algorithm can pinpoint the actual fault, as opposed to merely the faulty regions that are typically identified by strategies proposed in the literature. Also, analytical results suggest that it is an effective strategy that can be used to design highly dependable biochip systems.

A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems

Nano-Electro-Mechanical-Systems (NEMS) are a technological solution for building miniature systems which can be beneficial in terms of safety, efficacy, or convenience. Thus investigation is necessary for their usefulness in drug delivery. In order to be an effective and reliable implantable system the DDNEMS (Drug Delivery Nano-Electro-Mechanical-System) should have low power dissipation, fault tolerance, and reconfigurability capabilities. In this paper we introduce a DDNEMS architecture, identify its major components, and propose the design of the crucial component universal (voltage) level converter (ULC). The ULC is a unique component that will reduce dynamic power and leakage of DDNEMS while facilitating its reconfigurability. The ULC is capable of performing level-up and level-down conversions and can block an input signal. We have prototyped a ULC using 32nm high-k/metal-gate nano-CMOS technology with dual-VTh technique. The robustness of the design is tested by carrying out three types of analysis, namely: parametric, load and power. It is observed that the ULC produces a stable output for voltages as low as 0.35V and loads varying from 50fF to 120fF. The average power dissipation of the proposed level converter with a 82fF capacitive load is 5µW.

A fault detection and diagnosis technique for digital microfluidic biochips

With the miniaturized biochips finding applications in safety-critical applications dependability of these chips has become an important issue since the consequences of a malfunction of such as chip could be catastrophic. Thus, these chips have to be tested both after the manufacture as well as during field operations. In this paper we propose an integrated testing and diagnosis strategy for the digital microfluidic biochips that can locate single as well as a certain class of multiple defects. This can be used to increase chip yield and dependability of the biochips in the field operation.

Estimating correlation for a real-time measure of connectivity

There has recently been considerable interest in connectivity analysis of fMRI and scalp and intracranial EEG time-series. The computational requirements of the pair-wise correlation (PWC), the core time-series measure used to estimate connectivity, presents a challenge to the real-time estimation of the PWC between all pairs of multiple time-series. We describe a parallel algorithm for computing PWC in real-time for streaming data from multiple channels. The algorithm was implemented on the Intel Xeon™ and IBM Cell Broadband Engine™ platforms. We evaluated time to estimate correlation for signals recorded with different acquisition parameters as a comparison to real-time constraints. We demonstrate that the execution time of these efficient implementations meet real-time constraints in most instances.

Study of data locality for real-time biomedical signal processing of streaming data on Cell Broadband Engine

High performance computing is becoming critical in the medical area to aid real-time processing of complex analysis of biological signals. In this paper parallel schemes for real-time computations of pair-wise correlation (PWC) of electroencephalogram (EEG) signals, which belongs to streaming-data class of applications, are proposed and implemented and their performances are evaluated. Currently most of the EEG based diagnosis for epilepsy is done off-line. However, there is a growing need to perform these diagnoses in real-time to aid health care providers, including surgeons, in decision-making process that will lead to improved quality of life and prevent undesirable consequences, such as readmission to hospitals resulting in prolonged suffering and higher health care costs. Systematic study of the PWC problem and the IBM Cell Broadband Engine (CBE) architecture led us to a model that is well suited for the Cell architecture and GPUs. Measurements on the CBE indicate that speedup of 33.91 is possible over the serial code running on Intel Xeon processor and the schemes can be used for real-time signal processing.

Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer

The computationally intensive power flow problem determines the voltage magnitude and phase angle at each bus in a power system for hundreds of thousands of buses under balanced three-phase steady-state conditions. We report an FPGA acceleration of the Gauss-Seidel based power flow solver employed in the transmission module of the GridLAB-D power distribution simulator and analysis tool. The prototype hardware is implemented on an SGI Altix-RASC system equipped with a Xilinx Virtex-II 6000 FPGA. Due to capacity limitations of the FPGA, only the bus voltage calculations of the power network are implemented on hardware while the branch current calculations are implemented in software. For a 200,000 bus system, the bus voltage calculation on the FPGA achieves a 48x speed-up with PQ buses and a 62x for PV over an equivalent sequential software implementation. The average overall speed up of the CPU-FPGA implementation with 100 iterations of the Gauss-Seidel power solver is 2.6x over a software implementation, with the branch calculations on the CPU accounting for 85% of the total execution time. The CPU-FPGA implementation also shows linear scaling with increase in the size of the input power network.

A machine learning approach to modeling power and performance of chip multiprocessors

Exploring the vast microarchitectural design space of chip multiprocessors (CMPs) through the traditional approach of exhaustive simulations is impractical due to the long simulation times and its super-linear increase with core scaling. Kernel based statistical machine learning algorithms can potentially help predict multiple performance metrics with non-linear dependence on the CMP design parameters. In this paper, we describe and evaluate a machine learning framework that uses Kernel Canonical Correlation Analysis (KCCA) to predict the power dissipation and performance of CMPs. Specifically we focus on modeling the microarchitecture of a highly multithreaded CMP targeted towards packet processing. We use a cycle accurate CMP simulator to generate training samples required to build the model. Despite sampling only 0.016% of the design space we observe a median error of 6–10% in the KCCA predicted processor power dissipation and performance.