Bhaskar Chatterjee

Effectiveness and scaling trends of leakage control techniques for sub-130 nm CMOS technologies

This paper compares the effectiveness of different leakage control techniques in deep submicron (DSM) bulk CMOS technologies. Simulations show that the 3-5x increase in IOFF/mm per generation is offsetting the savings in switching energy obtained from technology scaling. We compare both the transistor IOFF reduction and ION degradation due to each technique for the 130nm-70nm technologies. Our results indicate that the effectiveness of leakage control techniques and the associated energy vs. delay tradeoffs depend on the ratio of switching to leakage energies for a given technology. We use our findings to design a 70nm low power word line driver scheme for a 256 entry, 64-bit register file (RF). As a result, the leakage (total) energy of the word line drivers is reduced by 3x(2.5x) and for the RF by up to 35%(25%) respectively.

Dual supply voltage clocking for 5 GHz 130 nm integer execution core

This paper describes dual-V/sub cc/ clocking on a 1.2 V, 5 GHz integer execution core fabricated in 130 nm CMOS to achieve up to 71% measured clock power (including 15% active leakage) reduction. A write-port style pass-transistor latch and split-output level-converting local clock buffer are described for robust, DC power free low-V/sub cc/ clock operation.

Leakage control techniques for designing robust, low power wide-OR domino logic for sub-130nm CMOS technologies

In this paper, we discuss the design of leakage tolerant wide-OR domino gates for deep submicron (DSM), bulk CMOS technologies. Technology scaling is resulting in 3-5x increase in transistor I/sub OFF///spl mu/m per generation resulting in 15%-30% noise margin degradation of high performance domino gates. We investigate several techniques that can improve the noise margin of domino logic gates and thereby ensure their reliable operation for sub-130nm technologies. Our simulations indicate that, selective usage of dual V/sub TH/ transistors shows acceptable energy-delay tradeoffs for the 90nm technology. However, techniques like supply voltage (V/sub cc/) reduction and using non-minimum L/sub c/ transistors are required in order to ensure robust and scalable wide-OR domino designs for the 70nm generation.

DFT for delay fault testing of high-performance digital circuits

Timing-only parametric defects are a major source of failures and test escapes in modern ICs. A DFT technique using compound domino logic gates with footer transistors uncovers these hard-to-detect defects with minimal performance and power overheads.

A 90 nm 6.5 GHz 256/spl times/64 b dual supply register file with split decoder scheme

This paper describes a 256/spl times/64 b 2-read, 1-write ported static register file for 6.5 GHz operation in 1.2 V, 90 nm CMOS. Read/write select drivers and decoder use 0.9 V lower supply to reduce total energy by 23%. Local/global bitlines use a leakage-tolerant split-decoder scheme with conditional precharge to achieve 65% (90%) higher DC robustness compared to conventional static (dynamic) bitline scheme.

A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies

In this paper we present the design of a high performance 32-bit ALU for low power applications. We use dual power supply scheme and CPL logic for non-critical units of the ALU. In addition, latches with only n-MOS clocked transistors are used to interface logic operating at different power supplies and achieve static power free operation. Our simulation results indicate that, for the 180 nm-65 nm CMOS technologies it is possible to reduce the ALU total energy by 18%-24%, with minimal delay degradation. In addition, there is up to 22%-32% reduction in leakage power in the standby mode.

A DFT technique for low frequency delay fault testing in high performance digital circuits

This paper presents a DFT (design-for-testability) technique for delay fault testing of high performance, dynamic CMOS circuits. A high performance, delay fault testable, 16 bit adder is designed in 0.18 /spl mu/m CMOS technology. Simulations for the adder demonstrate that this technique can detect delay faults greater than 35 ps and improves delay fault detection capability. It also allows at least 10/spl times/ reduction in test mode clock frequency. Furthermore, the proposed method is capable of providing delay fault diagnostics. However, the proposed DFT technique increases delay by 8.6% with minimal power penalty.

Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology

In this paper, we present the design of a 32-b arithmetic and log unit (ALU) that allows low-power operation while supporting a design-for-test (DFT) scheme for delay-fault testability. The low-power techniques allow for 18% reduction in ALU total energy for 180-nm bulk CMOS technology with minimal performance degradation. In addition, there is a 22% reduction in standby mode leakage power and 23% lower peak current demand. In the test mode, we employ a built-in DFT scheme that can detect delay faults while reducing the test-mode automatic test equipment clock frequency.

Modeling and designing energy-delay optimized wide domino circuits

In this paper, we present simple analytical models for energy (switching+short circuit) per transition and delay for wide-NOR domino logic gates. These gates are used to design register files (RFs) in high performance microprocessors and priority encoders for content addressable memory (CAMs). They contribute significantly to the overall switching energy and read delay, therefore require accurate modeling and optimized designing. Our results for a 130 nm bulk CMOS technology indicate that the energy (delay) models track SPICE simulations to within 4% (7%) for a large range of load and delay conditions. The results show that, optimal energy-delay operation is a function of the number of pulldown paths. It is achieved when the wide-NOR gate equivalent fan-out is between 2.3-2.7.

A DFT technique for delay fault testability and diagnostics in 32-bit high performance CMOS ALUs

Aggressive technology scaling has been the mainstay of digital CMOS circuit design for the past 30 years. This has resulted in the design of multi-gigahertz microprocessors with unprecedented levels of integration. However, this is posing serious challenges to IC testing and long-term reliability. A major source of failures and test escapes in high performance ICs can be attributed to timing-only parametric failures. We implement a DFT technique to detect delay faults in a full custom 32-bit high performance ALU. We present the energy-delay tradeoffs and scaling trends associated with our DFT technique for the 180 nm-65 nm CMOS technologies. In addition, we demonstrate how this technique can be used to detect delay faults with improved resolution (/spl sim/60 ps for 180 nm technology) at relatively low, test mode clock frequencies.