Manoj Sachdev

Comparative delay and energy of single edge-triggered and dual edge-triggered pulsed flip-flops for high-performance microprocessors

Flip-flops and latches are crucial elements of a design from both a delay and energy standpoint. We compare several styles of single edge-triggered flip-flops, including semidynamic and static with both implicit and explicit pulse generation. We present an implicit-pulsed, semidynamic flip-flop (ip-DCO) which has the fastest delay of any flip-flop considered, along with a large amount of negative setup time. However, an explicit-pulsed static flip-flop (ep-SFF) is the most energy-efficient and is ideal for the majority of critical paths in the design. In order to further reduce the power consumption, dual edge-triggered flip-flops are evaluated. It is shown that classic dual edge-triggered designs suffer from a large area penalty and reduced performance, prohibiting their use in critical paths. A new explicit-pulsed dual edge-triggered flip-flop is presented which provides the same performance as the single edge-triggered version with significantly less energy consumption in the flip-flop as well as in the clock distribution network.

A digitally programmable delay element: design and analysis

Variable delay elements are often used to manipulate the rising or falling edges of the clock or any other signal in integrated circuits (ICs). Delay elements are also used in delay locked loops (DLLs). Although, a few types of digitally controlled delay elements have been proposed, an analytical expression for the delay of these circuits has not been reported. In this paper, we propose a new delay element architecture and develop an analytical equation for the output voltage and an empirical relation for the delay of the circuit. The proposed circuit exhibits improved delay characteristics over previously reported digitally controlled delay elements.

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies

As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions. Standard functional tests often fail to detect unstable SRAM cells. Undetected unstable cells deteriorate quality and reliability of the product as such cells may fail to retain the data and cause a system failure. Special design and test measures have to be taken to identify cells with marginal stability. However, it is not sufficient to identify the unstable cells. To ensure reliable system operation, unstable cells have to be repaired. CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies covers a broad range of topics related to SRAM design and test. From SRAM operation basics through cell electrical and physical design to process-aware and economical approach to SRAM testing. The emphasis of the book is on challenges and solutions of stability testing as well as on development of understanding of the link between the process technology and SRAM circuit design in modern nano-scaled technologies.

Impact of self-heating effect on long-term reliability and performance degradation in CMOS circuits

As the technology feature size is reduced, the thermal management of high-performance very large scale integrations (VLSIs) becomes an important design issue. The self-heating effect and nonuniform power distribution in VLSIs lead to performance and long-term reliability degradation. In this paper, we analyze the self-heating effect in high-performance sub-0.18-/spl mu/m bulk and silicon-on-insulator (SOI) CMOS circuits using fast transient quasi-dc thermal simulations. The impact of the self-heating effect and technology scaling on the metallization lifetime and the gate oxide time-to-breakdown (TBD) reduction are also investigated. Based on simulation results, an optimized clock-driver design is proposed. The proposed layout reduces the hot-spot temperature by 15/spl deg/C and by 7/spl deg/C in 0.09-/spl mu/m SOI and bulk CMOS technologies, respectively.

A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability

We propose a quad-node ten transistor (10 T) soft error robust SRAM cell that offers differential read operation for robust sensing. The cell exhibits larger noise margin in sub-0.45 V regime and 26% less leakage current than the traditional soft error tolerant 12 T DICE SRAM cell. When compared to a conventional 6 T SRAM cell, the proposed cell offers similar noise margin as the 6 T cell at half the supply voltage, thus significantly saving the leakage power. In addition, the cell exhibits 98% lower soft error rate than the 6 T cell in accelerated neutron radiation tests carried out at TRIUMF on a 32-kb SRAM implemented in 90-nm CMOS technology.

Variation-Aware Adaptive Voltage Scaling System

Conventional voltage scaling systems require a delay margin to maintain a certain level of robustness across all possible device and wire process variations and temperature fluctuations. This margin is required to cover for a possible change in the critical path due to such variations. Moreover, a slower interconnect delay scaling with voltage compared to logic delay can cause the critical path to change from one operating voltage to another. With technology scaling, both process variation and interconnect delay are growing and demanding more margin to guarantee an error-free operation. Such margin is translated into a voltage overhead and a corresponding energy inefficiency. In this paper, a critical path emulator architecture is shown to track the changing critical path at different process splits by probing the actual transistor and wire conditions. Furthermore, voltage scaling characteristics of the actual critical path is closely tracked by programming logic and interconnect delay lines to achieve the same delay combination as the actual critical path. Compared to conventional open-loop and closed-loop systems, the proposed system is up to 39% and 24% more energy efficient, respectively. A 0.18-mum technology test chip is designed to verify the functionality of the proposed system showing critical path tracking of a 16times16 bit multiplier

Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs

Transient current testing (I/sub DDT/) has been often cited as an alternative and/or supplement to I/sub DDQ/ testing. In this article we investigate the potential of transient current testing in faulty, chip detection with silicon devices. The effectiveness of the I/sub DDT/ test method is compared with I/sub DDQ/ as well as with SA-based voltage testing. Photon emission microscopy is used to localize defects in several faulty, devices. Furthermore, the potential of I/sub DDT/ testing for leaky deep sub-micron devices is investigated.

Deep sub-micron I/sub DDQ/ testing: issues and solutions

The effectiveness of I/sub DDQ/ testing in deep sub-micron is threatened by the increased transistor sub-threshold leakage current. In this article, we survey possible solutions and propose a deep sub-micron I/sub DDQ/ test mode. The methodology provides means for unambiguous measurements of I/sub DDQ/ components and defect diagnosis. The effectiveness of the test mode is demonstrated with a real life example.

A method to derive an equation for the oscillation frequency of a ring oscillator

A new method for deriving an equation for the oscillation frequency of a ring oscillator is proposed. The method is general enough to be used for a variety of types of delay stages. Furthermore, it provides a framework to include various parasitic and secondary effects. The method is used to derive an equation for a common ring oscillator topology. The validity of the method and the resulting equation have been verified through simulation. The oscillation frequencies predicted by the proposed method are more accurate than existing equations and account for more secondary effects.

SRAM Cell Stability: A Dynamic Perspective

SRAM cell stability assessment is traditionally based on static criteria of data stability requiring three coincident points in DC butterfly curves. This definition is based on static (DC) characteristics of the cell transistors. We introduce the dynamic criteria of cell data stability knowing that the cell operates in a dynamic environment alternating between access and non-access conditions. The proposed definition of the dynamic data stability criteria introduces a new bound for the cell static noise margin (SNM). It reveals that the true noise margin of the cell can be made considerably higher than the conventional SNM once the cell access time is sufficiently shorter than the cell time-constant. This phenomena can be used to extend the noise margin in (partial) subthreshold SRAMs. Moreover, a simulation method for verification of the dynamic data stability criteria is presented. Silicon measurement results in 130 nm CMOS technology confirms the concept of dynamic data stability and designers ability to trade timing and static parameters . Finally, it is shown that the long time constant due to the subthreshold operation of the cell can be exploited to maintain data stability with proper choice of access and recovery time.