Bibhudatta Sahoo

Histogram Based Deterministic Digital Background Calibration for Pipelined ADCs

This paper presents a deterministic digital background inter-stage gain calibration technique for pipelined analog-to-digital converters (ADCs). The proposed method first estimates the inter-stage gains of the various stages of the pipelined ADC at power-up by conventional foreground digital calibration technique. It then estimates the maximum digital code at the output of each stage while digitizing the input signal during normal operation. A drift in the interstage gain during normal operation changes the maximum digital code which is estimated by the algorithm. The gain is estimated based on the fact that the ratio of the initial maximum code to the new maximum code is equal to the ratio of the initial gain to the new gain. Since thermal noise can corrupt the accurate estimation of the maximum digital code, an histogram based approach is used to find the maximum code. Unlike other digital background calibration techniques which either require training signals or require the input signal to have certain statistics, simulations show that this technique can accurately estimate the gain for sine wave, ramp, and random inputs having an amplitude as low as 18 dB below full-scale. Simulations also show that this technique is robust to parameter drift and circuit noise.

At speed digital gain error calibration of pipelined ADCs

This paper proposes a full speed digital gain error calibration technique for pipelined ADCs. The calibration takes care of both finite op-amp gain and capacitor mismatch. Unlike previous calibration techniques that use resistor ladder to generate the calibration signal, the proposed technique uses capacitors switching to reference voltages to eliminate the large RC time constants associated with resistor ladder. The proposed technique also facilitates the calibration to happen at full speed overcoming the drawbacks of existing foreground calibration techniques. 12-bit ADCs with first stage resolution of 1.5-bit, 2.5-bit, 3.5-bit, and 2-bit, followed by an ideal back-end ADC were simulated in system level using MATLAB and then at circuit level in Cadence. The circuit simulations incorporate various non-idealities like finite op-amp gain, op amp settling, and capacitor mismatch. Circuit level simulations in Global Foundrys (GF) 55-nm process with an an open loop op amp gain of 50 dB and capacitor mismatch of ±3% show that the calibration method improves the SFDR by more than 30 dB and SNDR by more than 25 dB.

An overview of digital calibration techniques for pipelined ADCs

As device dimensions and supply voltage are shrinking, the design of high-speed and high-resolution analog-to-digital converters (ADCs) is getting more and more challenging. Since the shrinking device sizes enable high-speed and low-power digital circuits, there has been a trend to use digital circuits to estimate and correct for the analog circuit nonidealities (i.e. calibrate) to realize high-performance ADCs. This summary paper enumerates some of the digital techniques that have been adopted in the past two decades to realize high-speed high-resolution pipelined ADCs, which are typically used in communication and imaging applications.

A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application

This paper proposes a wide dynamic-range lowpower signal conditioning circuit for low-side current sensing application. The proposed architecture uses a double sampling technique for switched capacitor programmable gain amplifier (SC-PGA) thus enabling the PGA to work at low frequency However, the analog-to-digital converter (ADC), which digitizes the amplified signal works at high frequency to achieve high dynamic range. The double sampling technique relaxes the slewrate and settling requirement of the op amp in the PGA. The switched capacitor implementation obviates the need for explicit level-shifting circuit while enabling rail-to-rail input common mode. The closed loop SC-PGA architecture is very robust to gain drift due to temperature and supply voltage variation. The design incorporates correlated double sampling technique to overcome offset and flicker noise. The analog-to-digital converter used in this design is a multi-bit second order ΔΣ-ADC [14]. The circuit is implemented in AMS 0.35 μm CMOS process with 3.3 V supply. Simulations show that the overall system, i.e., PGA and ΔΣ-ADC, achieves a dynamic range in excess of 80 dB while consuming 2 mA.

Radix based digital calibration technique for pipelined ADC using Nyquist sampling of sinusoid

This paper describes a new radix based calibration technique for pipelined analog-to-digital converters (ADCs). The proposed technique uses sinusoidal signal sampled at Nyquist rate to mitigate the effects of capacitor mismatch and finite op amp gain error that degrade the performance of a typical pipelined ADC. The calibration has been illustrated using a 1.5-bit per stage non-flipover topology. This technique is promising compared to the existing foreground calibration algorithms as it requires sinusoidal input which is easily available. Since this technique does the calibration at Nyquist rate it captures the finite op amp settling effect, which no other foreground calibration technique does. Behavioral simulations for a 12-bit pipelined ADC which has 11, 1.5-bit stages followed by 2-bit flash, validate the calibration technique.

Error feedback based noise shaping in a double sampled ADC

A first order error feedback based noise shaping in a double sampled ADC is proposed. This topology is ideal for nanometer CMOS technology, as it obviates the need for high-gain and high output-swing op amps and fast-settling, power-hungry, and noisy reference buffers. Using a one stage op amp with a gain of 70 (i.e. 37 dB) and output swing of ±75 mV , this topology, realized in GPDK 90-nm CMOS technology, achieves an SNDR of 60 dB operating at 1 GHz (effective sample rate of 2 GHz due to double sampling) with an OSR of 32.

A Digitally Assisted Radiation Hardened Current Steering DAC

This paper studies the effect of radiation on the performance of a 12-bit current steering digital-to-analog converter (DAC) and proposes a digitally assisted radiation hardening technique to overcome the performance degradation due to radiation. Circuit level simulations in UMC 65-nm SP process show that Signal-to-Noise Ratio (SNR) of the DAC falls from 74 dB to 41. 29 dB with radiation dose ranging from 0 to 100 Mrad and the proposed hardening technique overcomes this performance degradation.

A multi-pole single-tap IIR based DFE equalizer topology

Decision feedback equalizer (DFE) using finite impulse response (FIR) feedback filter forms the backbone of modern wireline communication receivers. Incorporating infinite impulse response (IIR) feedback filtering in DFE is an upcoming area of research owing to the inherent power efficiency of analog filtering. Till date, multiple pole IIR based DFEs have been primarily implemented using multiple, single-pole IIR filters. In this paper, we propose a new architecture that can replace multiple single-pole IIR filters with a single IIR which has multiple poles, thus saving area and power compared to its predecessors. The proposed architecture can be tuned for existing wireline channels whose pulse-responses are characterized by long tails. Simulations of the proposed architecture in 65-nm UMC65-SP show more than 50% improvement in eye height and more than 25% improvement in timing jitter for cascaded B12 and cascaded T12 channels at 8-Gbps.