Vineeth Sarma

Gating and Serializing the Data Path of CPU for Low Power Consumption

Data path is one of the major power consuming parts of the CPU. Low power high performance processors are the demands of the consumers. The current processors in the market provide enhanced performance, but the factor that we consider is the power consumption. The paper focuses on effective power conserving techniques in the data path including gating the data path and reducing the number of bus lines. Gating the data path can help in reducing the redundant calculations that cause wastage of power in normal processors. We also analyze the power consumption while reducing the number of bus lines in the data path. Our design is based on 32-bit ALU on the data path. We begin with 32-bit parallel inputs for ALU, and then reduce the input bus lines to 16, 8 and so on, until input serialization is achieved. The power variation that is brought about by reducing the input data lines is estimated using Xilinx ISE 10.1. The first section of the paper describes the parameters that are responsible for higher power consumption in bus lines. This is followed by details on gating the data path with the implementation of the ALU and the power estimation for all different configurations of data input lines. The last part of the paper consists of the results of power estimation for varying data input lines and the power comparison for a gated and a non-gated ALU.

Hardware Implementation of Low Power, High Speed DCT/IDCT Based Digital Image Watermarking

This paper presents a comparison with the conventional watermarking technique and the novel 5-stage pipelined implementation of DCT/IDCT which is used in digital image watermarking. The most common method of Discrete Cosine Transform (DCT)-based digital image watermarking which is used for image authentication and copyright protection is the transpose method. In this method the 2-Dimensional DCT is obtained by taking two 1-dimensional DCTs in series. The image pixel value is first divided into 8x8 blocks and the row-wise 1D DCT of each block is taken. The transpose of the blocks is then determined and a column-wise 1D DCT is ascertained which gives the 2D DCT of the data. The major advantage of this design is that, unlike the conventional DCT-based watermarking technique, this method uses a 5-stage pipeline which can bring about a speed increase of close to 500% over the conventional method which is naturally a great advantage. This technique has been tested on the standard ‘Lena’ image. Both visible and invisible watermarking is implemented in hardware. The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b. Matlab is used to produce the binary data file which is the input to the 1D DCT module. The hardware implementation is done in Xilinx XC3S4000 FPGA. The results of the comparison are discussed in the concluding sections.

At speed digital gain error calibration of pipelined ADCs

This paper proposes a full speed digital gain error calibration technique for pipelined ADCs. The calibration takes care of both finite op-amp gain and capacitor mismatch. Unlike previous calibration techniques that use resistor ladder to generate the calibration signal, the proposed technique uses capacitors switching to reference voltages to eliminate the large RC time constants associated with resistor ladder. The proposed technique also facilitates the calibration to happen at full speed overcoming the drawbacks of existing foreground calibration techniques. 12-bit ADCs with first stage resolution of 1.5-bit, 2.5-bit, 3.5-bit, and 2-bit, followed by an ideal back-end ADC were simulated in system level using MATLAB and then at circuit level in Cadence. The circuit simulations incorporate various non-idealities like finite op-amp gain, op amp settling, and capacitor mismatch. Circuit level simulations in Global Foundrys (GF) 55-nm process with an an open loop op amp gain of 50 dB and capacitor mismatch of ±3% show that the calibration method improves the SFDR by more than 30 dB and SNDR by more than 25 dB.

Novel Low Power, High Speed Hardware Implementation of 1D DCT/IDCT Using Xilinx FPGA

DCT/IDCT finds potent application in the field of image and signal processing. In this paper we concentrate on a novel five stage pipelined implementation, which consumes less power. The design uses Verilog HDL and is simulated in Modelsim 6.3b. Matlab is used to generate the data in binary format which serves as the input data and cosine values for computing 1D DCT/IDCT in HDL. There are other low power implementations as in [4], but in this novel implementation we prove that a lower power implementation can be done which also increases speed (of what?) by approximately five times over that of conventional implementations. The implementation of both non-pipelined (conventional) and pipelined method uses Xilinx XC3S4000 FPGA. The DCT/IDCT is found using the most common and optimum method of taking inputs as set of eight data elements [1], [2]. Finally, a comparison of the speeds of both implementations is made, and the speed up achieved by the low power pipelined implementation of 1D-DCT/IDCT is presented.

Error feedback based noise shaping in a double sampled ADC

A first order error feedback based noise shaping in a double sampled ADC is proposed. This topology is ideal for nanometer CMOS technology, as it obviates the need for high-gain and high output-swing op amps and fast-settling, power-hungry, and noisy reference buffers. Using a one stage op amp with a gain of 70 (i.e. 37 dB) and output swing of ±75 mV , this topology, realized in GPDK 90-nm CMOS technology, achieves an SNDR of 60 dB operating at 1 GHz (effective sample rate of 2 GHz due to double sampling) with an OSR of 32.

Thermal noise canceling pipelined ADC

High resolution pipelined Analog-to-Digital Converters (ADCs) exceeding 10-bits are thermal noise limited. Typically for low-power switched capacitor (SC) circuits, the thermal noise of the op amp is the dominant source of noise as compared to the switches. This paper proposes a thermal noise canceling technique for pipelined stages that cancels the thermal noise of the op amp. The technique involves capturing the noise by an auxiliary DAC and then canceling the noise in the signal path. Circuit level simulations are done in IBM 32 nm SOI process. A case study of thermal noise cancellation for various resolution pipelined ADCs is also done.

Achieving Theoretical Limit of SFDR in Pipelined ADCs

In pipelined analog-to-digital converters (ADCs), the spurious free dynamic range (SFDR) and signal-to-noise ratio depend strongly on the precision with which the interstage gain and capacitor mismatch terms are estimated using digital calibration techniques. This paper introduces a dithering-based calibration technique, which facilitates accurate estimation of the interstage gain and capacitor mismatch term with minimal hardware overhead, thus realizing pipelined ADCs that achieve the theoretical maximum SFDR. The proposed technique is validated both at system level using MATLAB and then at circuit level. A prototype 12-bit pipelined ADC operating at 500 MHz was designed in 55-nm global foundry LP-CMOS process. The prototype 12-bit ADC realized with op amp that have open-loop gains as low as 54 dB, but linearity ≈100 dB achieves an SFDR of 100.13 dB when calibrated using the proposed technique.

Serializing the data bus of the Sun OpenSPARC T1 microprocessor datapath for reduced power consumption

Power consumption in processors have become a major issue in these days. This paper considers an efficient technique of serializing the datapath to reduce the power consumption as in [1]. We use the 64 bit datapath of Sun OpensSPARC T1 processor. This processor has four basic blocks for data manipulations which along with the register file and the bypass logic forms the datapath. Serialization is applied to all the four blocks which are the shift, multiply, divide, and Arithmetic and Logic (ALU) blocks. Power estimation and analysis are done for ALU and multiply blocks. We have introduced a module called serializer which is included as part of the bypass logic, to serialize the data path. Serializing can be brought about without much compromise in the speed but this paper emphasizes on the reduction in power consumption. The modified, bit serialized datapath of OpenSPARC T1 is implemented in Verilog HDL. Power analysis of original, parallel datapath and the modified, bit serialized datapath designs of OpenSPARC is done using Xilinx ISE 10.1 Power Analyzer. The results are discussed at the end of this paper.