Bill Eklow

On effective TSV repair for 3D-stacked ICs

3D-stacked ICs that employ through-silicon vias (TSVs) to connect multiple dies vertically have gained wide-spread interest in the semiconductor industry. In order to be commercially viable, the assembly yield for 3D-stacked ICs must be as high as possible, requiring TSVs to be reparable. Existing techniques typically assume TSV faults to be uniformly distributed and use neighboring TSVs to repair faulty ones, if any. In practice, however, clustered TSV faults are quite common due to the fact that the TSV bonding quality depends on surface roughness and cleaness of silicon dies, rendering prior TSV redundancy solutions less effective. To resolve this problem, we present a novel TSV repair framework, including a hardware architecture that enables faulty TSVs to be repaired by redundant TSVs that are farther apart, and the corresponding repair algorithm. By doing so, the manufacturing yield for 3D-stacked ICs can be dramatically improved, as demonstrated in our experimental results.

IJTAG (internal JTAG): a step toward a DFT standard

The widespread use of the IEEE 1149.1 standard test access port as the interface for not only boundary scan but also for access to device-internal test features has led to a highly useful but highly fragmented opportunity for the test community. The need for a standard description of internal test features and protocols is elucidated, and the framework for the extension of the boundary scan standards as launched by the ad hoc IJTAG working group is described

On effective and efficient in-field TSV repair for stacked 3D ICs

Three-dimensional (3D) integration based on through-silicon-vias (TSVs) is rapidly gaining traction for industry adoption. However, manufacturing processes for TSVs have been shown to introduce new failure mechanisms. In particular, thermo-mechanical stress and electromigration introduce reliability threats for TSVs, e.g., voids and interfacial cracks, which can lead to hard-to-predict timing errors on critical paths with TSVs, thereby resulting in accelerated chip failure in the field. Burn-in for screening latent defects during manufacturing is expensive and its effectiveness for new TSV defect types has yet to be thoroughly characterized. We describe a reconfigurable in-field repair solution that is able to effectively tolerate latent TSV defects through the judicious use of spares. The proposed solution includes a reconfigurable repair architecture that enables spare TSV sharing between TSV grids, and the corresponding in-field repair algorithms. The effectiveness and efficiency of our proposed solution is evaluated using 3D benchmark designs.

IEEE P1687: Toward Standardized Access of Embedded Instrumentation

The effort to standardize a methodology for accessing embedded instrumentation as IEEE PI687 continues to progress. This paper captures the current state of mind of the IJTAG working group with respect to the framework built to date and presents a discussion of other issues on which decisions are pending. The key elements of an architectural description language, a procedural language, and a hardware interface scheme are all taking shape, but still have many details to complete. Since this is a snapshot taken during the standard development process, the final form of the draft standard may differ from what is described here; any feedback to the working group is welcome

On Effective Through-Silicon Via Repair for 3-D-Stacked ICs

3-D-stacked integrated circuits (ICs) that employ through-silicon vias (TSVs) to connect multiple dies vertically have gained wide-spread interest in the semiconductor industry. In order to be commercially viable, the assembly yield for 3-D-stacked ICs must be as high as possible, requiring TSVs to be reparable. Existing techniques typically assume TSV faults to be uniformly distributed and use neighboring TSVs to repair faulty ones, if any. In practice, however, clustered TSV faults are quite common due to the fact that the TSV bonding quality depends on surface roughness and cleanness of silicon dies, rendering prior TSV redundancy solutions less effective. Furthermore, existing techniques consume a lot of redundant TSVs that are still costly in the current TSV process. This inefficient TSV redundancy can limit the amount of TSVs that is allowed to use and may even become the obstacle to commercial production. To resolve this problem, we present a novel TSV repair framework, including a hardware redundancy architecture that enables faulty TSVs to be repaired by redundant TSVs that are farther apart, the corresponding repair algorithm and the redundancy architecture construction. By doing so, the manufacturing yield for 3-D-stacked ICs can be dramatically improved, as demonstrated in our experimental results.

Yield enhancement for 3D-stacked ICs: Recent advances and challenges

Three-dimensional (3D) integrated circuits (ICs) that stack multiple dies vertically using through-silicon vias (TSVs) have gained wide interests of the semiconductor industry. The shift towards volume production of 3D-stacked ICs, however, requires their manufacturing yield to be commercially viable. Various techniques have been presented in the literature to address this important problem, including pre-bond testing techniques to tackle the “known good die” problem, TSV redundancy designs to provide defect-tolerance, and wafter/die matching solutions to improve the overall stack yield. In this paper, we survey recent advances in this filed and point out challenges to be resolved in the future.

IEEE 1149.6 - a practical perspective

The IEEE 1149.6 standard was approved in March of 2003. The standard extends the capability of the IEEE 1149.1 standard to include AC-coupled and/or differential nets. These nets are predominant in multi-gigabit serial technology. This paper presents a short overview of the 1149.6 standard and the issues that it addresses. The paper discusses design, verification and test considerations that must be dealt with when implementing 1149.6 logic on a component or a board. Since 1149.6 addresses a problem that is in part analog in nature, there are several new issues that must be dealt with which are not covered in previous 1149 based standards. The paper discusses the nature of these issues and their impact on design, verification and test. The paper is intended to be tutorial, providing tips and techniques to allow the user to quickly understand and implement an 1149.6 based design.

Post-bond Testing of the Silicon Interposer and Micro-bumps in 2.5D ICs

2.5D integration is emerging as a precursor to stacked 3D ICs. Since the silicon interposer and micro-bumps in 2.5D integration can suffer from fabrication and assembly defects, post-bond testing is necessary for product qualification. This paper proposes and evaluates an interposer test architecture based on extensions to the IEEE 1149.1 Std. The proposed method enables access to interconnects inside the interposer by probing on the C4 bumps. It provides an effective test method for opens, shorts, and interconnect delay fault in the interposer. Moreover, micro-bumps can be tested through test paths that include dies on the interposer. HSPICE simulation results show that a large range of defects can be detected, diagnosed, and characterized using the proposed approach.

New Techniques for Accessing Embedded Instrumentation: IEEE P1687 (IJTAG)

There is an industry-wide initiative called IJTAG (I for Internal) that has been prompted by the fact that many device and board test engineers are using the IEEE 1149.1 test access port and its supporting hardware and instruction features to access a variety of device-internal instrumentation. The IJTAG initiative was started at ITC 2004 and is now supported by over 50 device design and test professionals from all sectors of the electronics industry. IJTAG was formed to control the proliferation of unusual uses and, in some cases, non-compliant design of the TAP, which culminated in the 2005 submission of a project authorisation request to the IEEE to standardise the new technology emerging from the study. The IJTAG initiative is now known as the IEEE PI687 draft standard for the access and control of instrumentation embedded within a semiconductor device. In the words of the PAR, this standard will develop a methodology for access to embedded test and debug features (but not the features themselves) via the IEEE 1149.1 test access port (TAP) and additional signals that may be required. The elements of the methodology include a description language for the characteristics of the features and for communication with the features, and requirements for interfacing to the features. This embedded tutorial describes the work carried out so far by the P1687 working group. The two presenters are members of the P1687 core group and they will reflect the very latest thinking of the group

IEEE 1149.6: a boundary-scan standard for advanced digital networks

AC-coupled high-speed differential signals have been a hole in the IEEE 1149.1 boundary-scan standard since its inception. In May 2001, a group formed to address this problem, resulting in the IEEE 1149.6 standard. Several members of the IEEE 1149.6 working group describe how the standard works and how it can test Gigabit Ethernet, Fibre Channel and more.