Jeff Rearick

Calibrating clock stretch during AC scan testing

Delay fault testing via AC scan is shown to suffer from test application problems that, if not accounted for, will cause a reduction in test quality. The problem of clock period stretching is demonstrated, and a novel circuit for calibrating this effect is described. Guidelines for AC scan test application on the tester to improve the quality of AC scan tests are presented, along with results from several large ASICs

IJTAG (internal JTAG): a step toward a DFT standard

The widespread use of the IEEE 1149.1 standard test access port as the interface for not only boundary scan but also for access to device-internal test features has led to a highly useful but highly fragmented opportunity for the test community. The need for a standard description of internal test features and protocols is elucidated, and the framework for the extension of the boundary scan standards as launched by the ad hoc IJTAG working group is described

A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and Testing

The performance of high-speed serial data links, along with the architectures of the transmitter and receiver circuitry used on either end, has led to increasing difficulty in applying traditional test and measurement techniques to characterize these channels. One solution, explored in this work, utilizes stimulus generation and response analysis circuitry embedded in the devices driving and receiving the links to perform a variety of tests and measurements that match and even exceed those possible with traditional instruments, as actual silicon results demonstrate. The access to this embedded measurement circuitry is provided via the IEEE std. 1149.1 test access port by use of a possible prototype for the draft IEEE P1687 (IJTAG) standard. This access mechanism is explained and its wider applications for test and debug are explored

IEEE P1687: Toward Standardized Access of Embedded Instrumentation

The effort to standardize a methodology for accessing embedded instrumentation as IEEE PI687 continues to progress. This paper captures the current state of mind of the IJTAG working group with respect to the framework built to date and presents a discussion of other issues on which decisions are pending. The key elements of an architectural description language, a procedural language, and a hardware interface scheme are all taking shape, but still have many details to complete. Since this is a snapshot taken during the standard development process, the final form of the draft standard may differ from what is described here; any feedback to the working group is welcome

First ic validation of IEEE Std. 1149.6

This paper provides proof of concept for the newly-approved 1149.6 standard by investigating the first silicon implementation of the test receiver. EXTEST and EXTEST/spl I.bar/PULSE tests were applied to functional channels as well as channels with a set of externally-induced hard defects. All valid signals were correctly received, and all defects were detected, thus validating both 1149.6s anticipated backwards compatibility with 1149.1 and fault coverage. Mission-mode tests showed no performance degradation due to the test circuits. Characterization across PVT of the test receiver suggests 1149.6s robustness with respect to noise.

Frequency detection-based boundary-scan testing of AC coupled nets

The use of AC coupling capacitors on high-speed interconnects prevents the use of traditional DC-based boundary-scan techniques to test for board manufacturing defects. A solution is provided by a novel scheme that makes use of frequency discrimination using simple digital circuits that are easily integrated with the 1149.1 boundary-scan standard. Simulation results are presented which show the effectiveness of this method, and its robustness and scalability are compared with alternative solutions.

Integrating boundary scan into multi-GHz I/O circuitry

A minimally invasive solution for adding boundary scan to high-speed I/O circuits is described. The insertion of boundary scan registers on the transmit side is done in the lower-speed parallel domain, while the boundary scan registers on the receive side is done using the techniques described in IEEE standard 1149.6 in the high-speed serial domain. Special clocking requirements are described, and results from actual silicon testing are presented that demonstrate negligible impact on functional performance while maintaining compliance with the both 1149.1 and 1149.6 standards.

A Survey of Test Problems and Solutions

The past two decades have seen a steady stream of challenges and responses in the test field. This paper surveys selected key problems and the progression of their solutions, in both topical and intrinsic aspects, with the aim of performing a meta-analysis of the nature of test innovation. The significant track record of success demonstrated by the industry will be put under serious pressure as technology advances