Bill Lane

A comparison of calibration methods based on calibration data size and robustness

Abstract Least squares (LS) regression, ridge regression (RR) and partial least squares (PLS) regression have been widely used in statistical calibration of near infrared (NIR) instruments. Comparison of these methods has attracted lots of interest in literature. However, most papers compare calibration methods on the basis of a single experiment and focus on “accuracy” rather than “robustness”. In “real life”, the average accuracy level of various calibration methods may not make that much of a difference, but having an extremely bad prediction may be unacceptable. As well, a calibration set may be very expensive to acquire and methods that work well on small calibration sets may be preferred. In this paper, we compare least squares regression, ridge regression and partial least squares regression in the context of the varying calibration data size. Three data sets used in this study are all NIR-based measurements of fat or protein in milk. For a given calibration data size, 100 simulation experiments are carried out, the average value and 95 percentile of the root mean squared prediction errors of each method are compared. We found that relative performance of the calibration methods depends on data set and calibration data size as well.

Fabrication and Characterization of Bi2Te3-Based Chip-Scale Thermoelectric Energy Harvesting Devices

Thermoelectric energy harvesters convert otherwise wasted heat into electrical energy. As a result, they have the potential to play a critical role in the autonomous wireless sensor network signal chain. In this paper, we present work carried out on the development of Bi2Te3-based thermoelectric chip-scale energy harvesting devices. Process flow, device demonstration and characterization are highlighted.

Test structure configurations for analysis of field effect influenced self-heating and thermal coupling in High Voltage SiGe HBTs

this paper presents several test structure configurations that facilitate a comprehensive assessment of self-heating and thermal coupling effects in High Voltage SiGe HBTs in a DTI on SOI process. Several layout test structures are investigated including variations in device separations, multi-device arrays and the influence of the substrate contact in the regions outside the trench isolation, and indeed the potential for trench field effects themselves, the latter two both due to the high voltages involved. The findings are reported with a view to focus on a Compact Modelling solution implementable in a commercial CAD tool.

The 36 V Bipolar:

This paper reports on the optimization of a 36 V complimentary bipolar design by using a new depletion mode field-effect architecture for the collector of the bipolar that greatly expands the boundary of the familiar tradeoffs. This achieves an n-p-n with a measured |β at 1 V x V_a at 18 V| = |270 x 1100 V|, a JfT at 1 V = 28.7 μAμm^-2, and |fT at 1 V x BV| = |2.6 GHz x 58 V|, with a p-n-p having a |β at 1 V x V_a at 18 V| = |250 x 800 V|, a JfT at 1 V = 27.0 μ Aμm^-2, and |fT at 1 V x BV| = |1.9 GHz x 69 V|. While these performance enhancements appear to offer a lot with little expense, they do serve to reveal an additional tradeoff between β x V_a x fT x BV x JfT and Linearity. This is where the curvature of the forward output characteristic curves quantified by the extrapolated Early voltage significantly changes over the voltage range |0-10 V|. Through the use of measured silicon results with calibrated TCAD simulations, the physics behind this depletion mode collector design is explained, and using this understanding, it ultimately shows how it is possible to limit the range of the associated nonlinear performance for low collector biases. Then, keeping linearity as a key performance target together with the field-effect architecture, the 36 V bipolar is rebalanced to achieve ann-p-nwitha|β at 1 V x V_a at 18 V x fT at 1 V x JfT at 1 V x BV x Linearity| = |270 x 220 V x 2.6 GHz x 28.7 μAμm^-2 x 47 V x (0.2-30 V) Linearity|, and a p-n-p with a |β at 1 V x V_a at 18 V x fT at 1 V x JfT at 1 V x BV x Linearity| = |185 x 180 V x 1.8 GHz x 27 μAμm^-2 x 45 V x (0.2-30 V) Linearity|.

\beta \times V_{a} \times \text {fT} \times \text {BV} \times \text {JfT} \times

A low-thermal budget (<450/spl deg/C), multilayer CMOS compatible, surface micromachining process has been developed to fabricate IR bolometers and microswitches for RF and automatic test equipment applications. While there is a significant body of literature on the characterisation of thin films of materials for MEMS applications, the published work deals mainly with films or structures of one material. This paper describes the work undertaken to characterise the elastic modulus and residual stress in films of individual dielectric and metal layers and results on composites of dielectric and metal. This paper considers the results obtained for structures composed of oxide, oxide-aluminium/silicon-titanium, oxide-titanium and titanium layers. Material properties are measured using cantilever and fixed beam arrays fabricated in oxide, metal and composite metal/oxide films. The parameters extracted are residual stress, stress gradient and elastic modulus.

Linearity Tradeoff

Abstract Misalignment of patterns between different masking layers of integrated circuit is becoming a limiting factor in achieving higher density circuits. A single test structure has been designed and developed to measure the amount of misalignment between various masking levels in CMOS/NMOS technology. Measurement is done electrically. The test structure can be implemented in the mask set of normal VLSI circuits as drop-in to evaluate misalignment of any combination of layers in the whole fabrication sequence.

Test structures for a MEMS SiO/sub x//metal process

This paper presents a Verilog-A compact model adaptation for a High Voltage SiGe HBT in a DTI on SOI process incorporating characteristic changes observed from a Field Effect Electrode. The output characteristics of the Bipolar are controlled, or “tuned”, by what is effectively an additional terminal. The model proposed is based on MEXTRAM and includes a new terminal node. The main additional effects are captured through the use of empirical formulae, while maintaining the bulk of the original code. The model is validated against DC and AC results from on-wafer Si test structures.

A new test structure for misregistration evaluation

Known to the power industry, there is an increasing functional safety need to isolate delicate control systems from the violent world of the Insulated Gate Bipolar Transistor (IGBT), which has resulted in a growing demand for Digital Isolators. This is where the gate control signal for the IGBT can be coupled across a dielectric barrier, while the barrier itself is capable of withstanding high working voltages and surge events. Preventing the formation of a complete integrated system solution for the end customer is the fact that while the control signal can be coupled across the isolation barrier - the transient power needed to drive the IGBT gate cannot. To solve that problem, this paper describes the development of an innovative IGBT architecture that targets the 1200V voltage node, has a first silicon VCE(SAT) = 2.7V at JC=10Amm-1, provides latch-up immunity, and critically has gate drive capacitances that are over two orders of magnitude smaller, at 0.58pF for every Amp of IGBT current, relative to conventional IGBT architectures that report values in the range of 70 - 150pFA-1 at 25°C. This low input capacitance opens the door for the gate of this IGBT to be directly powered by integrated magnetically coupled isolation coils. For future work, further optimization of the VCE(SAT), and transient switching times are required.

A Tunable bipolar: Investigation of effects and a MEXTRAM based VerilogA model adaptation of field effect electrode influenced high voltage sige HBTs

Chip-scale thermoelectric energy harvester designs based on Bi2Te3 are presented with a focus on improving power density per device area for applications exchanging heat with ambient air through a heat sink. Practical vacuum capping is found to be beneficial for improving energy density despite the additional shunt created by the bonding ring around the 10mm2 harvester chip. Optimized device performance is predicted to significantly exceed that of commercially available devices with much lower thermoelectric leg length.

Low gate drive IGBT enabling direct control through Digital Isolator power

Development of a surface micromachining process for commercial scale production of absolute pressure sensors necessitates the definition of inspection tests at each stage of the process and for the completed packaged product. The yield measurement described in this paper is for a Field Effect Transistor pressure sensor integrated into a CMOS process. This measurement can be divided into verification of the electrical and mechanical properties of the pressure device. This paper describes the development of a simple method for mechanical yield determination. The method is based on a visual inspection procedure where the interference rings observed under a conventional 5X/20X inspection microscope, are correlated with white light interferometry (wafer level and packaged devices) and Atomic Force Microscopy (AFM) (wafer level) measurements. The application of these two profiling methods is also compared in the paper. Based on this work a simple, low cost, automatic system for yield determination using standard equipment can be developed. Initial results from a software system for inspection automation are presented.